940 - Diamond: Timing: Why are there two trace reports in the Lattice software?

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• 212 - Diamond: Why do users have preference items in the trace report with 0 timing score?

  There are several reasons why users will see this happen: The timing constraint specified is covered by another timing constraint in the preference file. This is most often seen when the design has two related clocks. Trace will provide timing ...

• 2351 - All FPGAs: How do I check the timing of the paths across two clock domains in the trace report?

  Description: If the two clocks (clock1_c and clock2_c) have an obvious timing relationship in the design, the timing information for paths across the two clock domains will be shown in the trace report as long as you have added associated timing ...

• ECP5 / Diamond 3.14: Why does my design get a Map device oversize error related to PLL for LFE5U-12F in with Diamond 3.14, but completes map successfully in earlier releases of Diamond software?

  In Diamond version 3.14, there is a bug where it incorrectly limits the number of PLLs in the device to 0 for LFE5U-12F. Example error message: ERROR - (device oversize error). The number of PLL components needed (1) exceeds the number available. ...

• Lattice Diamond: How do i allow the tool to analyze the CDC from my design and view paths on Trace reports?

  Users must add in a CLKSKEWDIFF constraint in order for the tool to analyze the different clock domains. Without this constraint, the tool will not report/analyze any CDC from the trace reports.

• 1587 - Diamond: What are the different factors that affect device speed, temperature and voltage selection during software timing analysis?

  Software uses different temperatures and voltages for timing analysis based on the following factors: Commercial vs. Industrial Part selection.: Commercial part selection enforces the following DEFAULT temperatures for Setup and Hold analysis (based ...