Description:
When doing a 'map timing checkpoint' in ispLEVER, you might see the following message:
"1 potential circuit loop found in timing analysis"
Solution:
This message is related to conditions being met to latch in data where "potential" indicates that there may or may not be asynchronous circuit loops present. In order to find out more about where the potential circuit loops might be occurring:
A more thorough analysis will now be run to report the actual asynchronous timing loop paths (if any are found).