2592 - What does "potential circuit loops found in timing analysis" in trace report mean?
Solution:
The use of combinational loops has long been discouraged because this can cause significant stability and reliability problems in a design. The combinational loop behavior is usually dependent on the relative propagation delays of the loop's logic. Typically, combinational loops creep into a design to handle sticky asynchronous issues. A combinational loop is essentially the implementation of an implied or inferred latch. An inferred latch is an example of a combinational feedback loop because this function has to be built out of LUTs since there is no latch mode for the FPGA registers. When latches are implemented in LUTs, the timing analysis tool is not able to check the setup and hold time requirements on these circuits. Most design issues in which a combinational loop has been employed can be solved with a standard register, and the design will be more robust and stable. Combinational loop warnings are usually a result of "combinational" logic code that isn't strictly combinational. These Combinational loops are usually associated with an error in the "Case" structure or the "IF/Then/Else" structure. (e.g. an incompletely specified "case statement").
One suggestion is to keep registers in separate processes from combinatorial logic. This makes it easier to tell if the inferred latch is really an error. Investigate any combinational loops and implement a fix in your code to remove unintended latches, or redesign the circuit so that no latch is required.
With the default setting, the warnings can be found in .twr or .par report without the loop paths. To look into the loops, add -p option with the command of trce, such as
trce -v 10 -gt -sethld -sp 6 -sphld m -p -o mtch2ddph_mtch2ddph.twr mtch2ddph_mtch2ddph.ncd mtch2ddph_mtch2ddph.prf
Also, the parameter "Report Asynchronous Timing Loops" can be set to "True" which is located under Place and Route Trace in the strategy options.
After that, all the loops are displayed in the .twr report as follows.
Loop:
Name Fanout Delay (ns) Site Resource
ROUTE 2 0.632 R3C22A.F0 to R3C22A.B0 est_ph5_w_c_1
--------
0.632 (0.0% logic, 100.0% route), 0 logic levels.
Loop:
Name Fanout Delay (ns)Site Resource
ROUTE 2 0.632 R78C13B.F0 to R78C13B.B0 est_ph5_w_c_2
--------
0.632 (0.0% logic, 100.0% route), 0 logic levels.
Loop:
Name Fanout Delay (ns) Site Resource
ROUTE 2 0.632 R30C17B.F0 to R30C17B.B0 est_ph5_w_c_3
--------
0.632 (0.0% logic, 100.0% route), 0 logic levels.