5819 - Diamond: Why did TRACE not detect a violation in the LSR pin, but during simulation, it was detected?

The static timing engine does static timing analysis only.

The LSR pin is not a clock pin and the pulse width requirement on this pin must be guaranteed by the designer.

The static timing engine does not check for the pulse width on the LSR pin. Simulation is the proper way to verify that the signal meets the requirement.

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5819 - Diamond: Why did TRACE not detect a violation in the LSR pin, but during simulation, it was detected?

5819 - Diamond: Why did TRACE not detect a violation in the LSR pin, but during simulation, it was detected?

Related Articles

2292 - Diamond:&nbsp; Why is there a Timing Rule Check violation in the trace report on a ODDRX4B element&nbsp;for timing between the SCLK &amp; ECLK inside this element?

6017 - MachXO2: There are no timing parameters specified in the datasheet for the XO2 slice Flip-Flop (ex. CLK vs LSR recovery time, CLK vs LSR removal time, and LSR minimum pulse). Where can I find the timing values?

940 - Diamond: Timing: Why are there two trace reports in the Lattice software?

Lattice Diamond Programmer: WARNING in Linux OS - Drivers were not detected. Install the Lattice VM Drivers to access the JTAG Chain.<br>

ECP5 / Diamond 3.14: Why does my design get a Map device oversize error related to PLL for LFE5U-12F in with Diamond 3.14, but completes map successfully in earlier releases of Diamond software?

2292 - Diamond: Why is there a Timing Rule Check violation in the trace report on a ODDRX4B element for timing between the SCLK & ECLK inside this element?