6598 - Diamond: How do we solve timing violations from Dual Clock FIFOs or other memory modules?

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• 6789 - How can prohibiting the usage of dedicated clock resources help solve hold timing violations?

  Primary/Secondary routing resources have less delay and low skew compared to local/general routing. One of the reasons for having a hold violation is that the data path is reaching the latch/end/capture flop faster than the clock path. When ...

• 7263 - Lattice Diamond: Are the hold window analysis violations observed on the Timing Analysis View valid timing violations? Do users need to make sure that these are passing even though they are not blocking bitstream generation?

  Even though PAR timing did not show any timing violations, users/designers must check the Timing Analysis View for hold window violations. Hold Window analysis is only for boundary paths, i.e. paths involving input or output ports specified with an ...

• 6771 - Radiant 2023.2 SP1 or earlier: How can user handle clock-domain-crossing (CDC) paths timing violations between rvlclk and another clock of the design (clk)?

  These timing violations only occur if we use soft JTAG for Reveal. To handle this, user can use a set_false_path constraint between the clocks as these paths are invalid.

• 7028 - Lattice Radiant/Diamond: How does Synplify Pro infer a Single Clock or Dual Clock FIFO?

  The FIFO primitive is not inferable by our synthesis tool, in this case, if you implement FIFO logic it will always use LUTS/REGISTERS/FLOPS for its utilization. Users must have to instantiate the FIFO16K primitive for it to be utilized. In this ...

• 939 - Lattice Diamond: How can I block clock transfers in the timing analysis tool?

  A clock domain transfer or crossing occurs when one register in a data path is clocked by CLKA and one register by CLKB. To block this transfer from the timing analysis use the preference: BLOCK INTERCLOCKDOMAIN If you are looking to relax or analyze ...