PAC Designer
7505 - PAC Designer: Error: Kernel Mode driver is not loaded in a memory
Description: Since PAC-Designer is a legacy software, the Design Utility included in it has drivers that are only compatible with Windows XP and when invoked on other Windows Operating Systems, the error below will occur: Error: Kernel Mode driver is ...
2228 - PAC Designer: How to change the timer value when using an ABEL design?
When using an ABEL design for the Power Manager II devices, the XLAT_STIMER macro and the XLAT_PRESCALER macro are both only used for simulation. Changing these parameters will NOT affect the setting of the timers in the Power Manager II device ...
2196 - PAC Designer: If two PAC-Designer exception commands trigger at the same time which one has priority?
If user create several exceptions in the LogiBuilder code and they trigger at the same time there is no way to predict which exception will have priority. It becomes a race condition at this point. This is NOT recommended since the sequence may have ...
2175 - PAC-Designer / Power Manager II: POWR1014A is configured to use VMONx in window mode, but the logibuilder code does not simulate the over/under trip points correctly with the window mode enabled. How does the simulator handle the window logic?
Solution: The simulator does not simulate the window logic. The stimulus waveform provides the logical state of the window output (voltage in window = true, voltage outside window = false).
2039 - PAC Designer: Why does the Fitter report show some Flip flops as TFF and others as DFF for my design?
The Fitter in PAC-Designer can use either D type flip flops or T type flip flops in a design and will normally use which ever is most appropriate for the application. The design will function correctly regardless of which type of flip flops are used ...
831 - PAC-Designer: How do I convert my Logi-Builder design code to ABEL?
PAC-Designer: There are times when the user wants to convert the design to ABEL language to describe the sequence for a Power Manager. Start a simple sequence and add your timers and output states in LogiBuilder. Save the design Compile the design ...
830 - PAC-Designer: What is the best way to get started on using Lattice PAC-Designer Mixed Signal Software?
PAC-Designer: Is there an easy way to get started learning Power-Manager Devices and PAC-Designer? The first step is to download PAC-Designer from the web. The next step is to take a look at the example file directory. Use FILE, DESIGN EXAMPLES. This ...
1930 - PAC Designer: What causes a design to fail to compile with the error f38009 or invalid p38031?
There are two issues which may cause these errors with a design. The first is that in order to use an Output on the right hand side of a supervisory equation it must also be assigned a value somewhere in the design. It could be assigned in a step of ...
1896 - PAC Designer: How to resolve the issue of unable to view the simulation waveform window in PAC-Designer?
Make sure that your design is compiled and fitted successfully. Then check your project path / file (.pac) name. The naming convention in PAC-Designer software does not support spaces in its pathname or filename. This is because PAC-Designer is ...
1895 - PAC Designer: How to change the I2C Address of the ISPPAC1014A device using the I2C Utility within PAC-Designer?
Users cannot change the I2C address of the POWR1014A using the I2C utility. This only sets the address that gets used by the utility to communicate to the POWR1014A. The I2C address for the POWR1014A device is specified using the schematic sheet of ...
1853 - PAC Designer: What does the error message “The application has failed to start because the application configuration is incorrect. Reinstalling the application may fix this problem” mean when launching PAC Designer?
This error message typically occurs when a user does not have Microsoft's .NET framework set up correctly for their machine. The necessary components are also provided with PAC-Designer, and can be manually installed by running the file ...
1850 - PAC Designer: Does the PAC-Designer I2C utility work with the Lattice USB Download cable?
The PAC-Designer I2C utility for the POWR1220AT8 device will work with the Lattice USB Download cable when using the WindowsXP operating system. It will not work with Windows7 operating system at this time. This utility was created so that a user ...
688 - PAC-Designer: How to view the internal DAC settings within the ispPAC-POWR1220AT8?
PAC-Designer: Using PAC Designer: In the main schematic window, select the 'Edit' function on the top toolbar. Under this feature choose 'Edit Symbol'. The menu will display the features that are viewable or can be edited. This would be similar to ...
669 - PAC-Designer: What happens during the shutdown sequence in a LogiBuilder program? Do I have any control over what happens during the shutdown sequence?
Description: In PAC-Designer's LogiBuilder sequencing language, the BEGIN SHUTDOWN instruction functions primarily as a passive label, with statements before it created in an 'interruptible' state, and statements following created in a ...
651 - PAC-Designer: Why does my LogiBuilder design fail to compile? PAC-Designer fails with: F38009 Invalid Node assignment for signal 'pin assignment'.
PAC-Designer: PAC-Designer will issue this error message if an output is set to be controlled by I2C and that same output is used in a Boolean equation. The fitter drops the output macrocell from the resource list as I2C is controlling the pin. ...
1734 - PAC Designer / Power Manager II: How to implement a reset in the code?
Solution: The reset function can be assigned to an IN Input pin and an equation can be written in the Exceptions or in the Supervisory Logic section. Reset can be accompanied with a Timer and simple or complex equations can be used to activate it. ...
1648 - PAC Designer: How to resolve error: F38190 "Signal not found in either the #$PINS or #$NODES list."?
This is related to the compiler not finding the signals or nodes needed that are described in the code. This can occur if there are signals defined in the Supervisory Equations expecting feedback from a pin. The error occurs when trying to use I2C ...
2865 - PAC Designer: How to implement a latched output for the Power Manager Device?
In the PAC-Designer Software, users can use D Flip-Flop to implement a clocked latch. In the Logibuilder section of the PAC-Designer software, declare a registered D Flip-flop output using Supervisory Equations. The registered output can be assigned ...
1590 - PAC Designer: Why do the post-fit equations differ from my design equations using PAC-Designer?
Sometimes the relationship between input equations and post-synthesis/fit equations developed by PAC-Designer are not intuitively obvious. The synthesis and fitter systems are designed to optimally utilize the CPLD hardware. Some of the types of ...
2848 - PAC Designer Trim Configuration: if the Profile0 mode is changed from Closed Loop Trim (CLT) to I2C, does the calculated value of resistors change?
In the Trim Configuration of PAC-Designer software for the Profile0 Mode, the calculated value of resistors remains the same regardless of whether I2C or CLT is used. To have the correct resistor network between POWR1220AT8 and the DC-DC converter, ...
466 - PAC-Designer: How to connect the POWR6AT6 Trim-DAC control to an analog-digital converter (ADC)?
Solution: The control logic for each POWR6AT6 Trim-DAC output is automatically connected to the analog-digital converter (ADC) and the respective Voltage Monitor (VMON) input. This is done such that the voltage applied to VMON1 is converted by the ...
462 - PAC-Designer / Power Manager II: What is the Vbpz Selection in the Trim Configuration Options?
Solution: Vbpz stands for Voltage-bipolar-zero and represents the nominal DAC output voltage when the DAC is set to mid-scale (0x80). For most applications, this selection can be left to "Auto" and the "Calculate" button in the Trim Configuration ...
1490 - PAC-Designer: How do PAC-Designer's project archiving functions work?
PAC-Designer: It is often necessary to send a PAC-Designer design to a colleague, or save it in a revision database. Some device types, such as the Power Manager product families contain multiple files. To aid in organizing these files, PAC-Designer ...
1467 - PAC-Designer: How can I set up the simulation time in PAC Designer ?
PAC-Designer: To simulate a design with Lattice Logic Simulator, the design must first be entered or edited using both the schematic windows and the LogiBuilder Sequence Editor. Next, a stimulus file should be created or edited using the Waveform ...
2751 - PAC Designer: Can I access the Platform Manager IN5 and IN6 CPLD inputs from I2C in a PAC-Designer logic design?
Access for IN5 and IN6 from I2C is supported in PAC-Designer version 6.23 and later. The signals are available as inputs to the Boolean expression editor in the PAC-Designer logic view. The latest version of PAC-Designer is available at: ...
1452 - PAC-Designer: What should be the settings of the comparator when the VMON analog inputs are not used?
PAC-Designer: Unused VMON pins should be connected to the boards analog ground. The default trip point settings of 0.075 should be left as is.
1446 - PAC-Designer: In PAC Designer software what does NODEx mean in Pin Definitions?
PAC-Designer: NODEx are internal variables or registers and are not output pins. They can also be used to interact between different state machines. To access/rename an available node, keep Sequence and Supervisory Logic (CPLD) window active and ...
1445 - PAC-Designer: Is there a I2C hardware verification utility available in the tool?
Solution: Yes, there is. I2C hardware verification utilities are available and can be accessed via Tools ->Design Utilities in the PAC Designer. A parallel port programming/download cable can be used to test the features available with most Lattice ...
1437 - PAC-Designer: What does error message "Error ID 8: At least one output instruction is required with one write" means?
Solution: In general, Platform Manager/Power Manager applications drive one or more outputs. If the state machine has no outputs assigned, the compiler will generate the above error message. For successful compilation one or more outputs must be ...
2625 - Platform Manager II: Is there a limit to the number of state machines implemented in the POWR1220AT8 in PAC-Designer?
The PAC-Designer software limits the number of multiple state machines to 15. In practice the number of macrocells in the POWR1220AT8 will limit the number of state machines to much less. The number of macrocells used per state machine is strongly ...
1435 - PAC-Designer: While implementing state machine Sequencer Instruction in LogiBuilder, is there a way to create an Exception condition in Step 0?
Solution: Upon power-up of the device, the analog portion of the device performs an internal calibration. A successful calibration is indicated by activating the internal signal AGOOD to a logic 1. The Sequencer Step1, i.e. Wait for AGOOD, pauses the ...
1434 - PAC-Designer: Is there a way to simulate or analyze analog signals?
Solution: The simulation feature in PAC Designer is meant for assistance in functional verification of the logic implemented. However, it does not simulate or analyze any analog signals like VMON inputs or TrimDAC outputs. There is no provision to ...
2586 - PAC Designer: In the PAC-Designer TRIM block, why does the Vbpz value sometimes change when the EIA Resistor Standard is changed in the options menu?
Solution: The EIA resistor standard option sets the available resistor choices to the TRIM calculator. For example, EIA96 gives more resistor choices to the calculator then EIA24. The calculator compares the possible Vbpz values with different ...
2578 - PAC Designer: When using the File->Import command in PAC-Designer, what information is imported from the JEDEC file?
Solution:The JEDEC files generated by PAC-Designer contain two types of information: the analog feature configuration (example: VMON trip points) and the CPLD configuration. The analog feature configuration is imported to the .PAC project by the ...
275 - PAC-Designer: How do I change the Timers on a ProcessorPM-PM605?
Solution: The device is programmable and may change it if needed using PAC-Designer. By default, the shipped configuration is programmed to implement a Power Supply Supervisor, Reset Generator and Watchdog Timer. The timer functions for the watchdog ...
273 - PAC Designer: How to simulate a design with ProcessorPM-POWR605 device?
The following link provides information for Reference Design RD1056, titled "Watch-dog Timer and Reset Generation with ProcessorPM". The link has the documentation and the source code for the design that is pre-programmed into the ProcessorPM. The ...
2574 - PAC Designer: Is it possible to manually assign TRIM DAC output voltages to Power Manager II Devices, rather than using the trim configuration calculator?
Solution:It is possible to assign manual DAC codes to the different profiles of the Power Manager II TRIM DAC outputs. The menu interface for manual assignment can be found in the Edit->Symbol menu in the top level schematic view of PAC-Designer. The ...
2573 - PAC Designer: How does the DC-DC Converter library work with the TRIM resistor calculation in PAC-Designer when a project is opened but does not have access to the original DC-DC Converter library?
Solution: When a user creates a new item in the DC-DC Converter library an .XML file is created and saved in the "PAC-Designer\DCtoDC_Library" folder. Then when the user configures each Trim output, they must Import a DC-DC converter into the design ...
270 - PAC-Designer: How to implement multiple ispPAC-POWR1220AT8 Power Manager devices on a board?
Solution: There are several ways - in some cases the functions inside a Power Manager may be stand alone and not affect the other device controlling different supplies. In cases where there are zones or sections that need to get powered up and down, ...
2449 - PAC Designer; L-ASC10: During Trim configuration in PAC-Designer, I receive an error when calculating DAC settings for my target profiles. What can cause this?
Solution:The Trim calculation references settings which can be configured in the Trim Configuration Options menu. In some cases you can fix the errors by increasing the "Maximum Supply Adjustment Range" from the default value of 5%. In other cases, ...
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