2751 - PAC Designer: Can I access the Platform Manager IN5 and IN6 CPLD inputs from I2C in a PAC-Designer logic design?

• Related Articles

• 2865 - PAC Designer: How to implement a latched output for the Power Manager Device?

  In the PAC-Designer Software, users can use D Flip-Flop to implement a clocked latch. In the Logibuilder section of the PAC-Designer software, declare a registered D Flip-flop output using Supervisory Equations. The registered output can be assigned ...

• 2363 - PAC-Designer:&nbsp; Why does user design fail to compile with a Warning 1211: Generate NAF file failed?<br>

  If the user Power Manager II design fails to compile and gives a Warning 1211 in the error message window it may be caused by using spaces or periods in the project file name or path name. AHDL2BLF; ABEL-HDL Processor PAC-Designer 6.30 Copyright(C), ...

• 1490 - PAC-Designer:&nbsp;How do PAC-Designer's project archiving functions work?

  PAC-Designer: It is often necessary to send a PAC-Designer design to a colleague, or save it in a revision database. Some device types, such as the Power Manager product families contain multiple files. To aid in organizing these files, PAC-Designer ...

• 2310 - PAC-Designer:&nbsp; Why does my POWR1014A design fail to compile but not give an error message?

  If your Power Manager II design fails to compile and gives no error message it could be due to the use of periods or spaces in the project file name or the path name. Usually the failure message is produced immediately after starting the compile ...

• 1467 - PAC-Designer:&nbsp;How can I set up the simulation time in PAC Designer ?

  PAC-Designer: To simulate a design with Lattice Logic Simulator, the design must first be entered or edited using both the schematic windows and the LogiBuilder Sequence Editor. Next, a stimulus file should be created or edited using the Waveform ...