1452 - PAC-Designer: What should be the settings of the comparator when the VMON analog inputs are not used?

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• 1434 - PAC-Designer: Is there a way to simulate or analyze analog signals?

  Solution: The simulation feature in PAC Designer is meant for assistance in functional verification of the logic implemented. However, it does not simulate or analyze any analog signals like VMON inputs or TrimDAC outputs. There is no provision to ...

• 466 - PAC-Designer: How to connect the POWR6AT6 Trim-DAC control to an analog-digital converter (ADC)?

  Solution: The control logic for each POWR6AT6 Trim-DAC output is automatically connected to the analog-digital converter (ADC) and the respective Voltage Monitor (VMON) input. This is done such that the voltage applied to VMON1 is converted by the ...

• 2228 - PAC Designer: How to change the timer value when using an ABEL design?

  When using an ABEL design for the Power Manager II devices, the XLAT_STIMER macro and the XLAT_PRESCALER macro are both only used for simulation. Changing these parameters will NOT affect the setting of the timers in the Power Manager II device ...

• 2578 - PAC Designer: When using the File->Import command in PAC-Designer, what information is imported from the JEDEC file?

  Solution:The JEDEC files generated by PAC-Designer contain two types of information: the analog feature configuration (example: VMON trip points) and the CPLD configuration. The analog feature configuration is imported to the .PAC project by the ...

• 2751 - PAC Designer: Can I access the Platform Manager IN5 and IN6 CPLD inputs from I2C in a PAC-Designer logic design?

  Access for IN5 and IN6 from I2C is supported in PAC-Designer version 6.23 and later. The signals are available as inputs to the Boolean expression editor in the PAC-Designer logic view. The latest version of PAC-Designer is available at: ...