2625 - Platform Manager II: Is there a limit to the number of state machines implemented in the POWR1220AT8 in PAC-Designer?

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• 2574 - PAC Designer: Is it possible to manually assign TRIM DAC output voltages to Power Manager II Devices, rather than using the trim configuration calculator?

  Solution:It is possible to assign manual DAC codes to the different profiles of the Power Manager II TRIM DAC outputs. The menu interface for manual assignment can be found in the Edit->Symbol menu in the top level schematic view of PAC-Designer. The ...

• 2751 - PAC Designer: Can I access the Platform Manager IN5 and IN6 CPLD inputs from I2C in a PAC-Designer logic design?

  Access for IN5 and IN6 from I2C is supported in PAC-Designer version 6.23 and later. The signals are available as inputs to the Boolean expression editor in the PAC-Designer logic view. The latest version of PAC-Designer is available at: ...

• 1446 - PAC-Designer: In PAC Designer software what does NODEx mean in Pin Definitions?

  PAC-Designer: NODEx are internal variables or registers and are not output pins. They can also be used to interact between different state machines. To access/rename an available node, keep Sequence and Supervisory Logic (CPLD) window active and ...

• 1734 - PAC Designer / Power Manager II: How to implement a reset in the code?

  Solution: The reset function can be assigned to an IN Input pin and an equation can be written in the Exceptions or in the Supervisory Logic section. Reset can be accompanied with a Timer and simple or complex equations can be used to activate it. ...

• 2865 - PAC Designer: How to implement a latched output for the Power Manager Device?

  In the PAC-Designer Software, users can use D Flip-Flop to implement a clocked latch. In the Logibuilder section of the PAC-Designer software, declare a registered D Flip-flop output using Supervisory Equations. The registered output can be assigned ...