In the PAC-Designer Software, users can use D Flip-Flop to implement a clocked latch.
In the Logibuilder section of the PAC-Designer software, declare a registered D Flip-flop output using Supervisory Equations. The registered output can be assigned to have a flip-flop with D input, Asynchronous Reset, and Asynchronous Preset.
The Boolean Expression should be such that the output of the flip-flop would be fed back to the D input. Users can choose to Reset or Preset the output depending on different conditions desired by the logic design.
An example code below shows how a latch can be implemented:
EQ0 OUTx.D=OUTx
EQ1 OUTx.AP= <condition1> AND <condition2> OR <etc>
EQ2 OUTx.AR=<condition3> AND <conditon4> OR <etc>
For more details refer to the Pac-Designer Software manual available with the tool.
You can also get the User Manual by logging into the Lattice website --> Under Support --> Technical Support --> Click on Software Home--> Click on PAC-Designer Design Software--> User Manual --> On this page, under "Software Downloads & Documentation", Select "User Manual". Download the "PAC-Designer Software User Manual"