I/O (HPIO, WRIO)
7557 - Lattice MachXO2: How to connect the 'No Connect' NC pins of MachXO2 packages?
Description: The 'No Connect' (NC) pins of the MachXO2 packages are true NC, they are unbonded internally, the package pins/balls are floating, therefore the NC pins can be either left floating, connect to GND or VCC. However, care must be taken on a ...
5846 - All Devices: Can Lattice FPGA IO pins be left Floating?
Floating IO pin is not recommended. If IO pins are left floating, then the input transistors might fall outside of the saturation or cut-off region. As a result, the device could draw additional current and increase the device's power consumption. If ...
5322 - MachXO3: Can MachXO3 support HSTL18 IO standard?
HSTL18 standard is NOT supported in MachXO3. HSTL18 is only supported in MachXO2
4686 - iCE 40: What is the recommended value for pull-up resistor on the user I/O pin of <b><font face="Courier">iCE40</font></b> devices?
Solution: There is no recommended value for pull-up resistor on the user I/O pin, as it depends on the purpose of using the pin. If the pullup is to avoid keeping a pin floating, then any pull-up value is fine unless power is a requirement. In such ...
4657 - ECP2, ECP3, ECP5, MachXO, MachXO2, MachXO3: What is the permitted maximum undershoot/overshoot voltage of a particular device?
Description: Undershoot and overshoot of -2 V to (Vihmax +2) V is permitted for a duration of less than 20 ns. This applies to the following device families: ECP2, ECP3, ECP5, MachXO, MachXO2, MachXO3. For more information, refer to the Absolute ...
4773 - MachXO3: Does device support mixed voltage inputs?
Yes, MachXO3L/MachXO3LF devices support mixed voltage for LVCMOS and LVTTL inputs.
5393 - MACHXO2: what is the condition of I/O when powered down?
Description: MachXO2 devices are designed to ensure predictable behavior during power-up and power-down. During powerup and power-down sequences, the I/Os remain in tri-state until the power supply voltage is high enough (VCCMIN) to ensure reliable ...
4045 - iCE40 : What is the default status of I/O pins before the configuration of an iCE40 device?
The default status of I/O pins before the configuration of an iCE40 device is tri-stated with a weak pull-up to VCCIO.
3999 - ispMACH4000 : For ispMACH4000 devices, is the bus-keeper option a global constraint for all the I/Os? When configuring I/O as bus-keeper, what is the signal status on power up?
For the ispMACH 4000V/B/C/Z devices, the bus-keeper option is a global constraint for all I/Os. For ispMACH4000 ZE devices, it is available on per-pin basis. During power up, the I/Os are at default state. After the device enters user mode, the I/Os ...
1854 - MachXO: Why are there two different IOL/IOH values in the sysIO Single-ended DC Electrical Characteristics table of the MachXO Datasheet?
When we go closer to the rails, the amount of drive we need drops. So, at 0.2 V from the rail, you will see lower than the 4 mA, 8 mA, 12 mA, 16 mA drive. As per the datasheet, it should be lower than the 4 mA, 8 mA, 12 mA, 16 mA but higher than 0.1 ...
569 - ALL CPLD: Can changing the slew rate save power?
Description: Yes changing the slew rate can save uA dynamic power. This is a result of the signal transitioning faster between the Vil, Vih input thresholds. One warning the faster your edge rate the more SSO (Simultaneous Switching Output) and ...
3699 - iCE40LP: What is the output impedance of HCIOT_2 on the iCE40 LP1K device?
Description: Refer to the Input/Output Buffer Information Specification (IBIS) model for the V-I characteristics of the LVCMOS I/O pin on the iCE40 device. The lvc330IO model has the V-I curve values for different voltages, and you can use these ...
1033 - Do the unused I/O pins need to be grounded in a device?
Lattice devices have weak internal pull-ups on all I/Os. So the I/O pins which are not used in the design do not need to be grounded or connected anywhere. Some of Lattice devices have global setting for pull-ups on IOs like On, Off or Bus Hold, and ...
2895 - LatticeXP2: Why is the LVDS data not received correctly when the fail-safe resistors are added?
The problem may be related to the big fail-safe bias voltage (Vfsb) with the small fail-safe resistors that can cause the distortion on the duty of the LVDS input and increase jitter. It will worsen the correct sampling of the LVDS RX data especially ...
2602 - ECP3: Can we assign LVCMOS33 inputs in the same bank as SSTL15 outputs for a LatticeECP3 device?
Solution: In order to assign a 3.3V inputs to a 1.5 V bank on the top side of a LatticeECP3 device (Bank 0 and Bank1), turn off the PCICLAMP in Spreadsheet view for the respective bank. By default, the PCICLAMP is ON for all the banks and hence, ...
3614 - iCE40 LP/HX: Does the GBIN[n] pin directly drive the GBUF[n]?
GBIN[n] doesn't drive GBUF[n] directly. iCECube2 will automatically place it at the right location depending upon the package and type of net such as clock, reset, enable.
247 - Is an external pull up required on the MachXO SleepN pin?
The SleepN pin on the MachXO C devices is an enable for the internal regulator. When the SleepN pin is asserted low the regulator is turned off and the device is put in a low power state. An external pull up is recommended or you can tie the pin to ...
246 - MachXO: How is the TSALL pin used in the MachXO?
Solution: TSALL is a programmable IO which can be used to Tristate all IOs when asserted. To use TSALL in your design, instantiate the TSALL component as shown below: TSALL Verilog HDL Example (MachXO) TSALL TSALL_INST (.TSALL ()); TSALL VHDL ...
5572 - What is the ECP5 IOs state during Power ON and during Before POR?
Here is the ECP5 IO status during Power ON and during before POR:
1928 - [Power Manager 2] Do the I2C inputs on the ispPAC-POWR1014 have hysteresis?
Yes, a small amount of hysteresis (300mV) is designed into the inputs to increase their noise immunity. The logic thresholds are centered around ~1.4V when VCCD is powered from a 3.3V supply. Despite the presence of hysteresis, it is still important ...
2356 - LatticeECP3: Can I lock the dual-link 7:1 LVDS pins to the left and right sides of a LatticeECP3-17EA device?
Description: Yes. Lattice recommends placing the 7:1 LVDS RX or TX pins on the left or right side of a LatticeECP3 device. If they are locked to both sides, the edge clock should go to both sides through dedicated routing resources. A LatticeECP3 EA ...
2347 - MachXO2: Why does the Lattice software picks VCCIO bank voltages smaller than 3.3V when all my design IO buffers are of the 3.3V type?
Description:The situation above can occur when you set your IO buffer HYSTERESIS attribute to NA. You can normally set your IO buffer HYSTERISIS attribute using one of the three methods shown below: ispLEVER software: Start the Design Planner target ...
2330 - LatticeECP3: Can LatticeECP3 devices support sub-LVDS IO?
Description: LatticeECP3 devices do not directly support sub-LVDS IO. But LatticeECP3 can support sub-LVDS IO with an external termination circuit. Please refer to Sub-LVDS Signaling Using Lattice Devices (FPGA-TN-02028) Technical Note available on ...
1827 - LatticeECP3: Does it allow for a multiple I/Os be connected in parallel to have higher combined output current exceeding that of a single
I/O?
LatticeECP3 FPGA 3.3V or 2.5V LVCMOS output pin can support maximum 20mA source or sink current per I/O. In order to support higher current I/O, a user can connect multiple adjacent I/O pins together to produce combined higher source or sink current. ...
1825 - What is the recommended slew rate with less duty cycle variations?
The FAST or SLOW slew can cause as much as 5% duty cycle variation depending on the frequency and the load. The general recommendation is to use FAST slew rate for frequencies higher than MHz. At higher frequencies, FAST slew will show a more ...
5398 - iCEcube2: Can iCE40UP5k support tristates?
Solution: iCE40 devices do not support fabric based tristate implementation. Tri-states are implemented using SB_IO primitive (iCEcube2). When "Disable IO insertion" is selected in Synplify Pro, SB_IO primitives do not get added at the IO's and ...
1782 - MachXO: What is the IO state when VCC, VCCAUX reach the datasheet recommended levels but VCCIO has not?
From the datasheet: https://www.latticesemi.com/view_document?document_id=9922 Typical I/O Behavior During Power-up The internal power-on-reset (POR) signal is deactivated when VCC and VCCAUX have reached satisfactory levels. After the POR signal is ...
5390 - IceCube2 / iCE40 UltraPlus: Why are there only two I/O Bank options (top and bottom bank), on the iCEcube2 chip configuration dialog when there are three I/O Banks on the iCE40 Ultra/UltraPlus device?
Solution: There are three I/O banks: one top bank (Bank 0) and two bottom banks (Bank 1_SPI and Bank 2). For the I/O bank voltages: TopBank is the voltage option for Bank 0. BottomBank is the voltage option for Bank 2. Voltage for Bank 1_SPI should ...
2263 - LatticeECP3: What is the proper use of termination resistors and internal coupling with the Lattice Serdes?
Current Mode Logic (CML) buffers are used as the common interface to the SERDES/PCS. Internal input and output terminations are provided to simplify board level interfacing and AC coupling capacitors are available within the CML receiver. These allow ...
5368 - MachXO3LF: How do you generate internal Vref generator in the device?
Solution: Internal Vref Generator is not supported on MachXO3. MachXO3 SysI/O Usage Guide FPGA-TN-02056 was initially referenced with MachXO2 SysI/O Guide FPGA-TN-02158 which supported Vref generator for SSTL and HSTL buffer types. However, this is ...
1758 - MachXO2: Can the MachXO2 device support PCI-compliant signaling on any GPIO?
Yes. However, there are considerations to keep in mind when choosing pins. The MachXO2 implements two aspects of PCI buffers independently: PCI-level compliant inputs/outputs PCI complaint internal clamps. MachXO2 implements PCI-level compliant ...
883 - How to change the emulated LVDS resistor network to get other output voltage levels?
The following table lists 1% resistor values to use when the VCCIO is set to 2.5V and the IO output current setting is 8ma: Differential mV Rseries Rparallel 191 301 118 217 261 121 266 210 127 310 178 133 357 150 140 417 124 150 478 105 162 ...
879 - LatticeXP2: How can I drive mini-LVDS output on LatticeXP2 if mini-LVDS IO standard is not available?
If user's design is using 50 ohm PCB trace and cable impedances, user can set the LatticeXP2 IO output type to LVDS and this will produce 400mv peak signal swing at the receiver's 100 ohm termination with proper common mode output voltage. The ...
7160 - iCE40 Ultra/UltraLite: What are the configurable I/O pull-up resistance values for iCE40?
Description: This article describes the 4 different configurations available for iCE40. Solution: There are 4 configurations for the pull up resistor of the iCE40: - 3P3K for 3.3kohm - 6P8K for 6.8kohm - 10K for 10kohm - 100k for the WEAKPULLUP This ...
5268 - In CrossLink, Can the hard-dphy pins be used as GPIO instead of dphy?
No, Hard-DPHY IOs in Crosslink are dedicated pins, cannot be used as GPIO.
1741 - MachXO2: I don't see Differential 3.3v CMOS inputs (LVCMOS33D) input characteristics in the MachXO2 Data Sheet.What are its specifications?
The LVCMOS33D buffer characteristics are similar to those of the LVDS33 differential input buffer, with these key differences: Vinp/Vinm = 0v min, 3.4v max, 3.3v typ Vcm = 2.6v max, 1.65v typ Fmax = 136MHz Note: The 100ohm internal termination ...
2185 - [MachXO] For the MachXO's Idk (hot socketing leakage spec), what factors control whether the Idk is sourced or sink?
The phenomena is a spike which occurs when ramping a pad above and below VCCIO. There is a circuit which controls the NWELL voltage of the PMOS driver. The NWELL tracks VCCIO when the pad is below VCCIO and the NWELL tracks the PAD voltage when the ...
7150 - IO for Nexus FPGAs: How to set the IO standard to "subLVDS" in GPIO option that is not included in DDR_Generic IP generation?
The 'subLVDS' option is not available in the IP GUI but user can set "subLVDS" in Device Constraint Editor (DCE) IO_TYPE for proper implementation of subLVDS in this IP.
2157 - [LatticeECP3] Will the LatticeECP3's read datavalid generation circuit work properly when I remove the VTT termination from the DQS pad?
The datavalid generation circuit works properly as long as you provide the READ pulse input to the DQSBUF block in the right timing. LatticeECP3 devices have preamble detection function which is a level detection circuit instead of edge detection. ...
2994 - MachXO2: If the device is not yet programmed, it will be booted in Default Mode Feature Row. Will the INITn pin automatically be used as an input? And can I (accidently) block the configuration of the FPGA by pulling INITn low?
The INITn pin of MachXO2 device when erased (Default Mode Feature Row state) is disabled. So you should be protected from accidently blocking the configuration by pulling INITn low.
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