5368 - MachXO3LF: How do you generate internal Vref generator in the device?

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• 619 - What is the detailed power-up sequence for a MachXO device?

  The following is the power-up sequence for a MachXO device: - All IOs trisate with a weak pull up - POR (Power On Reset) for internal circuitry asserted - Vcc and Vccaux reach minimum recommended datasheet levels - POR (Power On Reset) for internal ...

• 247 - Is an external pull up required on the MachXO SleepN pin?

  The SleepN pin on the MachXO C devices is an enable for the internal regulator. When the SleepN pin is asserted low the regulator is turned off and the device is put in a low power state. An external pull up is recommended or you can tie the pin to ...

• 725 - Does the MachXO device family support true LVDS buffers?

  The larger two devices (LCMXO1200 & LCMXO2280) in the MachXO family support True LVDS I/O. To set up "true LVDS" on the input side, connect a 100 ohm terminating resistor across the 'true' and 'compliment' input terminals. On the output side, no ...

• 739 - What is the default I/O state in a blank MachXO device?

  The silicon default of a bulk-erased MachXO device is as follows: Inputs are enabled, and referenced to Vccio. Buskeepers default to pullup. Outputs are tri-stated and default to 8ma at Vccio=1.8V and slow slew.

• 655 - How is the Global Set Reset (GSR) used in a design? Do I need to use the GSR symbol or component in my design to use the GSRN pin for the MachXO device?

  For the Lattice MachXO device, all the registers in the device will be reset upon power-up of the device, provided the power-up sequence is clean. This will happen without any additional effort on the part of the user. The software will evaluate the ...