3999 - ispMACH4000 : For ispMACH4000 devices, is the bus-keeper option a global constraint for all the I/Os? When configuring I/O as bus-keeper, what is the signal status on power up?

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• 2045 - [ispMACH 4000]: I have 75 5V inputs to an ispMACH 4000 device. Which I/O type should I use between LVTTL or LVTTL_5V?

  Description: Two 5V support options, “PCI_5V” and “LVTTL_5V” were added to the supporting I/O type constraint list for the ispMACH™ 4000 device families. Since the LVTTL I/O type's maximum VIH is 3.6V, you must use the LVTTL_5V I/O type to support 5V ...

• 3740 - ispMACH 4000: What is the difference between "External feedback" and "internal feedback" when calculating Fmax for ispMACH 4000 devices?

  When calculating the Fmax , the following two cases are considered 1. Internal feedback 2. External feedback When the signal is fed back through the GRP (global routing pool) without going through an IO pad, it is internal feedback whereas when it is ...

• 2142 - [ispMACH 4000]: What is the reason behind the high supply transients during startup for the ispMACH 4000 device?

  High transients during startup are because of supply sequencing used on the board, resulting in temporary leakage in the I/O buffer of the device. To minimize the transient current during power-on, configure the CPLD I/Os to a pull-up or float state. ...

• 1033 - Do the unused I/O pins need to be grounded in a device?

  Lattice devices have weak internal pull-ups on all I/Os. So the I/O pins which are not used in the design do not need to be grounded or connected anywhere. Some of Lattice devices have global setting for pull-ups on IOs like On, Off or Bus Hold, and ...

• 5645 - MachXO2/MachXO3 :Are there any power supply sequence requirement for MachXO2 and MachXO3 devices?

  POR is controlled by VCC and VCCIO0. As such, these banks should be brought up first. The typical I/O behavior during power-up is described below: The internal power-on-reset (POR) signal is deactivated when VCC and VCCIO0 reach VPORUP level. This is ...