569 - ALL CPLD: Can changing the slew rate save power?

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• 565 - Does reducing drive strength save power?

  Reducing drive strength can be used to save dynamic power. The savings will be in the uA range. Reducing drive strength will improve Simultaneous Switching Output (SSO).

• 1825 - What is the recommended slew rate with less duty cycle variations? <br>

  The FAST or SLOW slew can cause as much as 5% duty cycle variation depending on the frequency and the load. The general recommendation is to use FAST slew rate for frequencies higher than MHz. At higher frequencies, FAST slew will show a more ...

• 5884 - All FPGA: How I can generally compare the difference between SLOW and FAST of the SLEW RATE settings?

  Description: Using the RAMP data in the IBIS you can compare the Slew Rate between SLOW and FAST, try to understand the document using the notes and legends provide especially "Naming Conventions" in the upper part of the document and be able to read ...

• 5948 - Platform Manager 2 &amp; L-ASC10: What is the Power ramp rate for L-ASC10?

  Power supply ramp rates for all Vcc and Vccio has a minimum of 0.01 V/ms and Maximum of 100 V/ms, as indicated in page 06 of document: FPGA-DS-02036 The VCCA, VCC, VCCIO0, VCCIO1, and VCCIO3 pins should be connected to the same power supply, as also ...

• 843 - What can I do to maximize the emulated LVDS data rate? <br>

  Emulated LVDS will have maximum data rate near the device FMAX_IO frequency value if: the IOs are complimentary LVCMOS outputs (or have low timing skew) the IOs have similar rise and fall times the emulated LVDS output resistor network is placed ...