Description: LatticeECP3 devices do not directly support sub-LVDS IO. But LatticeECP3 can support sub-LVDS IO with an external termination circuit. Please refer to Sub-LVDS Signaling Using Lattice Devices (FPGA-TN-02028) Technical Note available on ...
Solution: TSALL is a programmable IO which can be used to Tristate all IOs when asserted. To use TSALL in your design, instantiate the TSALL component as shown below: TSALL Verilog HDL Example (MachXO) TSALL TSALL_INST (.TSALL ()); TSALL VHDL ...
The larger two devices (LCMXO1200 & LCMXO2280) in the MachXO family support True LVDS I/O. To set up "true LVDS" on the input side, connect a 100 ohm terminating resistor across the 'true' and 'compliment' input terminals. On the output side, no ...
The LatticeECP3 doesn't have a dedicated control signal to put the FPGA IO to tri-state. There are cases that some designers might want to have the LatticeECP3 FPGA IO tri-stated when a new line card is being inserted as some partner devices in these ...
Solution: iCE40 devices do not support fabric based tristate implementation. Tri-states are implemented using SB_IO primitive (iCEcube2). When "Disable IO insertion" is selected in Synplify Pro, SB_IO primitives do not get added at the IO's and ...