1827 - LatticeECP3: Does it allow for a multiple I/Os be connected in parallel to have higher combined output current exceeding that of a single I/O?

LatticeECP3 FPGA 3.3V or 2.5V LVCMOS output pin can support maximum 20mA source or sink current per I/O. In order to support higher current I/O, a user can connect multiple adjacent I/O pins together to produce combined higher source or sink current. So, the answer is yes however there are some restrictions and recommendations of using the combined FPGA I/O pins.

The average DC current drawn by I/Os between GND connections, or between the last GND in an I/O bank and the end of an I/O bank, as shown in the logic signal connections table shall not exceed n * 8mA, where n is the number of I/Os between bank GND connections or between the last GND in a bank and the end of a bank.

The FPGA design should guarantee that all the connected output pins switch simultaneously. It is highly recommended that all the connected output pins should be set for the same I/O type with the same output drive current and the FAST slew rate setting, and driven by the same signal with the minimum internal routing skews from the signal to each output pin.

It is recommended to add a 33ohm serial resistor per output pin. The serial resistors are physically placed close to the output pins. The serial resistors can prevent an intermittent short-circuit condition if one or more connected output pins drive high while the others drive low.

A user should be aware of the potential simultaneous switching noise caused by the combined high current I/Os and take precautions means to reduce the interference level of the simultaneous switching noises. The group of output pins connected in parallel should be physically placed adjacent to the VCCIO or GND. Don't place any sensitive I/O pins next to the simultaneously switching output pins.

LatticeECP3 I/O Protocol board adopts this solution by connecting three I/O pins in parallel to produce high current I/O for DAC application. This solution can also be used by any other FPGA/CPLD design which requires high current I/O. For more details of the board design, please refer to "High Current I/O" section and the schematics of the LatticeECP3 I/O Protocol Board - Revision C User's Guide.

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1827 - LatticeECP3: Does it allow for a multiple I/Os be connected in parallel to have higher combined output current exceeding that of a single I/O?

1827 - LatticeECP3: Does it allow for a multiple I/Os be connected in parallel to have higher combined output current exceeding that of a single I/O?

Related Articles

2233 - LatticeECP3:&nbsp; How to avoid a DQ output from becoming a PLL input when moving from a lower to a higher density device?

2005 - LatticeECP3:&nbsp; How do I select between the&nbsp;two Vol Max values 0.4V, or 0.2V&nbsp;documented in the&nbsp;LatticeECP3 device datasheet sysI/O Single-Ended DC Electrical Characteristics? &nbsp;

1033 - Do the unused I/O pins need to be grounded in a device?

5983 - Platform Manager 2: How many external DC-DC can be connected with GPIO output?

6502 - Certus-NX: What is the Maximum Current per bank?

2233 - LatticeECP3: How to avoid a DQ output from becoming a PLL input when moving from a lower to a higher density device?

2005 - LatticeECP3: How do I select between the two Vol Max values 0.4V, or 0.2V documented in the LatticeECP3 device datasheet sysI/O Single-Ended DC Electrical Characteristics?