Delay Cell
5582 - Platform Manager: How to add a Real Time Clock (RTC) with a Fault Logger for ECP5 using Platform Manager 2?
Description: This article describes adding Real Time Clock (RTC) with a Fault Logger for ECP5 using Platform Manager 2. Solution: The Full-Featured Fault Logger Configuration for ECP5 has several additional features for Timestamp. One of these is the ...
5289 - ECP5/ECP5-5G: Why ECP5 SERDES REFCLK must be at 100 MHz when TXPLL is set to 25x mode?
The 25X isn’t a hard restriction but PCIe with 100 MHz refclk is the only use case the factory considered so it was the only one that got documented. 25X mode is supported for all protocols. It was listed as PCIe because this is the common use for ...
3014 - How can shift register delay be optimized?
Often in designs, data path delays are implemented with the shift registers. Long delays require many shift registers, which consume a significant FPGA register resources. In many cases, using RAM-based shift registers will improve resource ...
655 - How is the Global Set Reset (GSR) used in a design? Do I need to use the GSR symbol or component in my design to use the GSRN pin for the MachXO device?
For the Lattice MachXO device, all the registers in the device will be reset upon power-up of the device, provided the power-up sequence is clean. This will happen without any additional effort on the part of the user. The software will evaluate the ...
619 - What is the detailed power-up sequence for a MachXO device?
The following is the power-up sequence for a MachXO device: - All IOs trisate with a weak pull up - POR (Power On Reset) for internal circuitry asserted - Vcc and Vccaux reach minimum recommended datasheet levels - POR (Power On Reset) for internal ...
578 - How do I use the ispMach4000 global clocks?
Global clock signals are low skew signals which save macrocells and routing resources when taken advantage of. Use your clocks like normal in your design. Note these cannot be gated clocks. Next using the Constraint Editor connect them to the global ...
1152 - Will Lattice FPGA's allow me to drive primary clock signal also drive on the edge clock?
Yes, can do this for the for the LatticeECP2/M, LatticeECP3, and LatticeSC/M FPGA devices. If you have a Primary clock signal that you also want to use to drive an edge clock, use the "PRIMARY2EDGE" preference. This will insure that the software ...
1151 - What is the best way to divide a clock by 2 in Lattice devices?
There are several different ways you could divide an incoming clock signal by 2. You could use the internal clock divider that is provided in the LatticeECP2/M, LatticeXP2, and LatticeSC/M FPGA devices. The LatticeECP2/M and LatticeXP2 each have 2 ...
565 - Does reducing drive strength save power?
Reducing drive strength can be used to save dynamic power. The savings will be in the uA range. Reducing drive strength will improve Simultaneous Switching Output (SSO).
543 - Do Lattice FPGAs support Spread-Spectrum Clocking (SSC)?
There are two aspects to SSC support: SSC generation and SSC reception. Only the LatticeSC family provides SSC generation support. Refer to TN1099, "LatticeSC sysCLOCK PLL/DLL User’s Guide" for more information (search for "spread spectrum"). ...
1100 - How can I use the complimentary outputs in Lattice FPGAs?
Most Lattice FPGA devices provide a complimentary output feature which allows a single ended buffer to provide its compliment on a different pin without using any FPGA logic resources or user routing. To enable this complimentary path the user needs ...
1085 - Is ac-coupling ok to use in your application?
A series-connected DC-blocking capacitor(a.k.a ac-coupling) is a commonly used method to change the DC bias level when interconnecting different devices and boards. AC coupling is a simple high-pass filter that has the disadvantage of degrading the ...
2705 - How to infer Block RAMs in iCE40 devices?
The iCE40 devices contain RAM4K modules , the number of RAM4K modules depends upon the device density. The Block RAMs can be easily inferred by writing standard HDL codes for Single Port and Dual Port RAM. You can check the placer.log file obtained ...
1066 - What are the hardware default settings of the ECP2/M sysCONFIG ports?
Basically, all the sysCONFIG pins have hardware default settings as standard LVCMOS IO configuration after power-up. When sysCONFIG pins act as driver, they are 8ma drivers when VCCIO8 @3.3V/2.5V/1.8V. They become 4ma pull up when VCCIO8 @1.5V/1.2V ...
1063 - How many seondary clocks are supported per region of ECP2/XP2 devices?
The ECP2/XP2 devices support region-based secondary clocks. There are total 8 secondary clock lines (SC0 - SC7), but only four of them (SC0 - SC3) can be used as Secondary Clocks (including CLK, CE and LSR controls), the other four lines (SC4 - SC7) ...
1052 - How to set LatticeECP3 FPGA IO in temporary tri-state when another partner device in line card doesn't support hot swap?
The LatticeECP3 doesn't have a dedicated control signal to put the FPGA IO to tri-state. There are cases that some designers might want to have the LatticeECP3 FPGA IO tri-stated when a new line card is being inserted as some partner devices in these ...
445 - When I measure the Power Manager II HVOUT voltage it is low, why?
Most likely the scope probe or volt-meter has too low an impedance and is pulling the voltage down. For example, if the High Voltage Output (HVOUT) is programmed to source 12 uA and the scope probe used to measure the output voltage is 100k to ...
1012 - Will all speed grades of the LatticeECP2/M and LatticeECP3 support the SerDes at 3.125 Gbps?
Yes, the SerDes/PCS is an embedded block and the performance is independent of speed grade. Only the FPGA core logic is affected by speed grade.
443 - Can I read the value of NODES in the POWR1014/A via I2C?
The NODES in PAC-Designer for the POWR1014/A do not have any I2C registers associated with them and therefore cannot be read directly via the I2C interface. If the NODE is routed to an actual output (HVOUT1-2 or OUT3-14) then the value of the NODE ...
1011 - Does each quadrant of the device have equal logic resources?
The answer is no. Clock trees are placed by quadrants, but LUTs are placed according to available space. In the ECP2M devices, the SERDES alone can take up to 1/4 of a quadrant. Thus, there is less logic resources physically present in that quadrant ...
442 - Can I read the value of NODES in the POWR1220AT8 via I2C?
The NODES in PAC-Designer for the POWR1220AT8 do not have any I2C registers associated with them and therefore you cannot directly read value of NODES via the I2C interface. If the NODE is routed to an actual output (HVOUT1-4 or OUT5-20) then you can ...
433 - How can I sense current with a Power Manager II?
The Power Manager II devices can not measure current directly. However, the Application Note AN6049 shows several circuits that can be used with a Power Manager II device to measure current. The circuits shown convert the current into a voltage that ...
429 - Does input threshold of an IO pin depend on Vcco value?
The short answer is no. The input threshold is ratioed based on internal voltages. If device power supply, Vcc, stays within the recommended operating range as specified in the device data sheet, the internal reference voltage remains the same and so ...
413 - How do I implement Power-Off Detection in a Power Manager II device ?
The Power Off Detection is used to sense when a supply (or set of supplies) is fully discharged before re-cycling the power-on or re-start sequence. Many devices require the supplies to be fully off before applying power and a Power Off Detection ...
1605 - Does default IO behavior change from device family to device family?
The IO behavior of each Lattice device family could be unique. Some of the device families support pull and bus keeper circuitry for each individual pin, some support such function on a global basis, while others have different pull condition for ...
3881 - Is it possible with the signal 'ENABLE_OUTPUT' of the primitive SB_IO (IO primitive of the iCE40) to create a bi-directional Low Voltage Differential Signalling (LVDS) IO?
No. the signal 'ENABLE_OUTPUT' of the primitive SB_IO (IO primitive of the iCE40) cannot be used to create a bi-directional LVDS IO. One has to use two separate pairs of IOs for LVDS Tx and LVDS Rx.
406 - Where is the Reset pin for the Power Manager II - POW607 ?
The POWR607 has a power down feature so that when the device is powered back up (using the IN1 pin) the sequence restarts at power up. If a more traditional reset function is desired, then IN1 (or any other input pin) can be used in the LogiBuilder ...
405 - Does the VCCPROG pin have to be powered to program the Power Manager II - POWR1220AT8?
The VCCPROG pin only needs power if the POWR1220AT8 is going to be programmed in circuit with the rest of the board powered down. This pin is provided as a programming option and should not be powered up when VCCD and VCCA are powered up. The ...
975 - What is the state of Flip Flop outputs at power-up? The reset pins of my design registers are tied to neither GSR nor LSR
Even if you do not use the GSR/LSR logic in RTL, GSR is always used during bitstream download. During bitstream download all flip flops are held at reset until the download is completed. So, the state of a register's Q output is always '0' or LOW at ...
972 - How is the FIXEDDELAY attribute used and implemented in Single Data Rate (SDR) mode in a LatticeECP3 device?
In SDR mode, the DELAYB has a fixed value calculated by the tool. This value will compensate for the delay from the input clock buffer through the primary or secondary (no edge) clock network to the input CLK pin of the input IO register. The DELAYB ...
2590 - Why do I see a glitch on the I/O during power up?
The default IO termination for many older Lattice devices (such as MachXO, ispMach4000) is pull up. When the device is powering up/down, the IO will ramp up/down following the IO power supply. If the IO voltage is monitored using a scope it will look ...
384 - Why are termination resistors required for DDR2 and DDR3 when the LatticeECP3 has an on-die termination (ODT) feature?
The LatticeECP3 ODT (On-Die Termination) was implemented originally for DDR3 interface support. During the validation process, we found that the internal VTT coupling noise negatively affects signal integrity of data pads with some specific data ...
970 - How do I implement edge clock routing from a Primary IO (PIO) in a LatticeECP2/M device?
You need to locate an input buffer in a dedicated site that supports direct access to the edge clock spine. This applies to PIOs that clock special elements like IDDR/ODDR as well as CLKDIV blocks. Typically, you need to specifiy an EDGE preference ...
1563 - How can I implement the tri-status buffer driven by the output of ODDRXD1 in ECP3 ?
To implement the tri-status buffer driven by the output of ODDRXD1(the output DDR for DDR generic mode in X1 gearing), you should use OFD1S3AX(a primitive used to implement DDR and DDR2 DQ tri-state) to generate OE signal for the tri-status buffer, ...
880 - The LatticeXP2 device does not have a sub-LVDS output type, can I still drive sub-LVDS inputs with the LatticeXP2?
Situation: An application uses the LatticeXP2 device and needs the sub-LVDS output type. Solution: Given that sub-LVDS signaling requires Vod from 100mv (min) to 200mv (max) and Vcm from +0.75v (min) to +1.05v (max), the sub-LVDS output type can be ...
843 - What can I do to maximize the emulated LVDS data rate?
Emulated LVDS will have maximum data rate near the device FMAX_IO frequency value if: the IOs are complimentary LVCMOS outputs (or have low timing skew) the IOs have similar rise and fall times the emulated LVDS output resistor network is placed ...
3829 - In an iCE40LP-CM81 device, can an internal oscillator be used as a clock source in the RTL design?
An internal oscillator can not be used as a clock source in the RTL design. It is only used for the device configuration.
826 - What is different about the ProcessorPM-POWR605 relative to the other Power Manager devices from Lattice?
The ProcessorPM-POWR605 is factory programmed to implement a power supply supervisor, Reset Generator and Watchdog Timer. The POWR605 is preloaded with a factory supplied design. Jumpers are provided that permit you to change the timing of the reset ...
1406 - How can I implement multiple Power Manager II devices on a board?
There are several ways to implement multiple Power Manager II devices on a board. In some cases the functions inside a Power Manager II may be stand alone and will not affect the other device controlling different supplies. In cases where there are ...
819 - How can I create a 10 second timer in an ispPAC-POWR1220AT8 device?
Background: The maximum Timer setting in the ispPAC-POWR1220AT8 device is 1966.08 ms. If you would like to use a longer timer then you must create a counter to accumulate timer pulses and use the counter output to indicate the time sequence. To ...
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