1063 - How many seondary clocks are supported per region of ECP2/XP2 devices?

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• 2251 - LatticeECP3:  Why only 7 out of 8 Secondary clocks can be assigned in a clock region for LatticeECP3 devices?

  In an LatticeECP3 family of devices, only 7 out of 8 SECONDARY clocks are available. One of the SECONDARY clocks does not go to the clock input of registers in the fabric. It only goes to clock enable or set/reset pins. So, the SECONDARY clocks are ...

• 2082 - LatticeECP3: How to effectively use secondary region clock in LatticeECP3 devices?

  Description: For LatticeECP3 devices, there are a total of 8 SECONDARY clocks. Each of the SECONDARY clocks can be further divided into REGION clock. The SECONDARY clocks are divided into different sized REGIONs depending on the device density. For ...

• 2390 - LatticeECP3: Can all Tx PLL clocks of SERDES drive the primary clock routing directly?<br>

  Description: No, only the Tx PLL half/full rate clocks in channel 0 of each SERDES quad may drive the primary clock routing directly. Eight primary clocks(CLK0~CLK7) may be used for LatticeECP3 devices. To drive the primary clock routing directly: ...

• 6502 - Certus-NX: What is the Maximum Current per bank?

  Description: The maximum 64 mA per bank (8 IO with 8 mA) applies when selecting # of IO switching simultaneously. If desired is to use 16 mA with 8 IO switching, the overall junction temperature will be 2X higher. The source and sink current will ...

• 7055 - All Nexus: What pins are preferred for output clocks?

  For input clocks, we can only used dedicated clock pins, PCLK or GPLL input pins for PLL reference clock. For output clocks, any IO pin can be used. There is no restriction for this.