To implement the tri-status buffer driven by the output of ODDRXD1(the output DDR for DDR generic mode in X1 gearing), you should use OFD1S3AX(a primitive used to implement DDR and DDR2 DQ tri-state) to generate OE signal for the tri-status buffer, place OFD1S3AX in output registers in Spreadsheet View of Design Planner, and place the clock signal on dedicated clock pin or use the primary clock resource for the clock. From LatticeECP3 High-Speed I/O Interface you can see more technical details.
The following code in Verilog shows an example of the implementation
OFD1S3AX OFD1S3AX_inst(
.D(oe_pre_dly),
.SCLK(clk),
.Q(oe)
)/* synthesis syn_noprune=1 */;
wire q_from_oddr;
oddr_aligned oddr_inst(
.clk ( clk ),
.clkout ( ),
.da ( data ),
.db ( data ),
.q ( q_from_oddr )
)/* synthesis syn_noprune=1 */;// exemplar attribute oddr_aligned dont_touch true
assign dataout = !oe ? q_from_oddr : 1'bz ;
where oddr_aligned is a DDR_GENERIC generated in IPexpress.