5289 - ECP5/ECP5-5G: Why ECP5 SERDES REFCLK must be at 100 MHz when TXPLL is set to 25x mode?

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• 2263 - LatticeECP3:  What is the proper use of termination resistors and internal coupling with the Lattice Serdes?

  Current Mode Logic (CML) buffers are used as the common interface to the SERDES/PCS. Internal input and output terminations are provided to simplify board level interfacing and AC coupling capacitors are available within the CML receiver. These allow ...

• 2381 - LatticeECP3: How do I implement an external reference clock for SERDES?<br>

  Description: The sources of external reference clocks for SERDES can be: Primary Clock pad (PCLK) FPGA PLL Since the extra jitter caused by the FPGA resources to route the clock to the SERDES will be passed onto the transmit data, care must be taken ...

• 1904 - [ispClock 5400D] Are ispClock products suitable for ITU-T G.8262 applications?

  No. Although ispClock products have excellent jitter specifications, the dynamics of their PLLs are very different from those used in data transmission applications (such as those based on ITU-T G.8262). The key difference is in PLL loop bandwidth. ...

• 2475 - Why must I use a Primary Clock Input for a clock instead of a general purpose pin?

  Lattice recommends always using Primary Clock (PCLK) inputs for clocks. An exception is when a clock input is routed directly to a single PLL then a dedicated PLL input should be used. If multiple PLLs are using the same input clock then a PCLK Input ...

• Can Avant Global Set/Reset Resources be analyzed through the Static Timing Analysis Tool on Radiant?

  Global Set/Reset resources cannot be analyzed in static timing analysis tool for both Nexus and Avant devices. For usage concerns and implementation of the mentioned resource, Users may refer to Global Set/Reset Usage for Nexus Platform App Note ( ...