MIPI CSI-2 / DSI D-PHY Receiver
7601 - Crosslink & MIPI D-PHY:
How do I deal when I update the MIPI virtual channel aggregation with the latest version, I got an issue with my hardware where I cannot get an image in the stream?
Solution: Please use the old version IP. We have tested it with the following IPs: RX v1.3 and TX v1.2. The design seems functional based on the first tests. At the time it was developed sometime in 2019, using Hard D-PHY RX might cause simulation ...
6648 - MIPI D-PHY:<div>Is it possible to connect two MIPI interfaces (2-lane input MIPI + 2-lane output MIPI) to the CertusPro-NX Versa Evaluation Board using the available connectors?</div>
Definition: Please use the FMC connector to utilize soft DPHY implementation. In the FPGA-EB-02046 CertusPro NX evaluation board, you may change the Bank supporting High Performance intended for FMC (Bank 3, 4, or 5) to 1.2V. To do this, you must ...
5879 - CrossLink: How to configure the Reference Design MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge for DSI single lane?<div><br></div>
Please refer to FPGA-RD-02060 Section 3, Design and Module Description. On the project file, modify the rx_dphy which is declared under rx/rx.sbx. On the Receiver section of the IP, modify the RX Interface to DSI and the Number of RX Lanes to one.
5271 - ECP5/ECP5-5G: What maximum MIPI High Speed (HS) can the Lattice ECP5 IO support?
The Lattice ECP5 IO can support High Speed of up to 576 Mb/s (range may vary).
3664 - MachXO2: When implementing MIPI CSI2 RX interface, can Bank 2 Vccio be connected to 3.3V instead of 2.5V?
Bank 2 having the LVDS inputs for the MIPI CSI2 RX interface can have the Vccio connected to 3.3V. Refer to 'sysIO Differential Electrical Characteristics' for LVDS under the 'DC and Switching Characteristics' section of the MachXO2 datasheet.
3636 - MachXO2: RD1146 states that the LP pins need to be HSTL18, the DPHY reference document RD1182 also says the LP pins should be 1.2V. Which one is correct?
Description: MIPI CSI2 RX interface RD1146 was the first to be introduced and the termination scheme used for that was using HSTL18 for the LP signals. The D-Phy(RD1182) was introduced later and the termination scheme optimized and superseded the ...
5263 - CrossLink: In soft MIPI DPHY RX, should the clock be placed only on PCLK pins? and Can the clock also be placed on MIPI_CLK/GR_PCLK/GPLL pins?
The Clock should be placed only on PCLK pins and they cannot be placed on MIPI_CLK/GR_PCLK/GPLL pins. Only following pins may be used for MIPI CLK: PCLKC2_0, PCLKT2_0, PCLKC2_1, PCLKT2_1, PCLKC1_0, PCLKT1_0, PCLKC1_1 & PCLKT1_1. Also, The tool will ...
5962 - CSI-2/DSI D-PHY Rx v1.4/CrossLink: What should be done if there are plenty of "0x00" inserted after SoT (=0xB8) during simulation?
Recommended to use Dual Clock as implementation of Rx FIFO. This should resolve the issue of many 0x00 as mentioned.
6798 - MIPI for CertusPro-NX/CrossLink-NX: What is the maximum CSI RX Bandwidth?
Please refer to aggregated bandwidth: CertusPro-NX: (softIP: sysIOx3 banks ==> 1.5Gbps 4lane x 3 ports ==> 18Gbps) Crosslink-NX: (hardIP: 2 ports ==> 2.5Gbps 4lane x 2 ports ==> 20Gbps) + softIP ==> (total 38Gbps)
5919 - MIPI D-PHY to CMOS Interface Bridge Soft IP: Why do I get this error message like this: "ERROR - IO register/latch csi2_to_cmos_inst/inst1_inst/lv_ff cannot be implemented in PIC."?
Description: This is caused by forcing a register whose input is being traced to be implemented as an input flip-flop because of a preference, USE DIN. Solution: The user should allow the register to be implemented as an internal flip-flop by ...
5892 - CrossLink: new CSI-2/DSI DPY Receiver IP version v1.3, however why I have many unconstrained input_setup paths and how can to avoid this?
Please check if this can improve or remove the unconstraint path by providing the timing preferences under Spreadsheet view settings for ip_csi_receive_clk_byte_o under the INPUT_SETUP section. You may provide the Time and Hold Time for this.
6519 - MIPI CSI-2 / DSI D-PHY Receiver: What is the use of the RX_FIFO in the MIPI D-phy RX IP?
Description: RX_FIFO is used when clk_byte_fr_i and clk_byte_o does not have the same frequency and/or is not synchronous, therefore it is used in order for the clocks to be synchronized and run at the same frequency. Nowfor the FIFO we introduce the ...
6517 - [Crosslink-NX & MIPI CSI2/DSI- DPHY]: What is the Max Line Rate of Crosslink-NX Soft Dphy for each package for -8 Speed Grade?
Definition: LIFCL17 72 WLCSP: 1250 Mbps LIFCL17 72 QFN: 1000 Mbps LIFCL17 121 CSFBGA: 1200 Mbps LIFCL17 256 CABGA: 1200 Mbps LIFCL40 72 QFN: 1000 Mbps LIFCL40 121 CSFBGA: 1200 Mbps LIFCL40 256 CABGA: 1200 Mbps LIFCL40 289 CSBGA: 1200 Mbps LIFCL40 400 ...
6516 - CrossLink-NX / MIPI CSI-2/ DSI D-PHY:What are the Max line Rate (Mbps) of Soft Dphy for Each Package for -9 Speed Grade?
Definition:LIFCL17 72 WLCSP: N/A (No -9 Speed Grade) LIFCL17 72 QFN: 1250 Mbps LIFCL17 121 CSFBGA: 1500 Mbps LIFCL17 256 CABGA: 1500 Mbps LIFCL40 72 QFN: 1250 Mbps LIFCL40 121 CSFBGA: 1500 Mbps LIFCL40 256 CABGA: 1500 Mbps LIFCL40 289 CSBGA: 1500 ...
6512 - [MIPI CSI-2/ DSI D-PHY RX]Could you tell me about method to calculate of MIPI Rx IP's FIFO depth?
Solution: There is no specific formula being followed in setting up the packet delay and fifo depth. What is advised is to apply similar concept to rate, time, and distance. Where the goal is to make READ and WRITE run at same speed, or atleast Write ...
6149 - Crosslink: In dphy_rx_wrap_beh.v, how do user resolve error related to port size mismatch?
- In dut_inst.v and dut_inst.vhd, the lp_hs_state_d_ port should be lp_hs_state_d_0. - In rx_dphy.v, the following should be inputs: input lp_d0_tx_en_i, input lp_d0_tx_p_i, input lp_d0_tx_n_i.
6140 - Crosslink: Is there any CSI-2 test pattern generator?
In Crosslink IP, Lattice do not have color bar pattern generator except for cmos-to-dphy IP but you may try to check MIPI CSI-2 Transmit Bridge Reference Design for other Lattice FPGA devices. Here's the link: ...
6946 - What is the spec of 'sync_clk_i' of MIPI D-PHY Rx IP? Does the signal require to be in synced with any other clocks?
Description: Spec is given that 'sync_clk_i', or the 'Sync clock frequency', can support 24-200Mhz, and it is defaulted to 60Mhz, based on CSI-2/DSI D-PHY Rx IP Core IPUG 02081 document. 'syn_clk_i' does not need to synchronize with any clocks, and ...
5636 - MachXO2/MachXO3 : Can I use XO2/XO3 to bridge multiple cameras?
There are hardware limitations with XO2 and XO3 devices for this particular application. Please check our existing solution which is the "4 Input to 1 Output MIPI CSI-2 Camera Aggregator Bridge". It allows you to interface to multiple MIPI CSI-2 ...
6114 - Crosslink NX : Are there any Reference Designs of DPHY for different applications as stated below? 1. Connecting Soft DPHY Rx module output to Soft DPHY Tx module input. 2. Image acquisition from a camera through Hard DPHY.
Solution: The following RDs available for Crosslink-NX will support the said applications: 1. FPGA-RD-02212 : N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation - Aggregate multiple Image Sensors into a single Output with Minimal Latency. - Uses ...
5621 - Crosslink: Can Hard-DPHY receive SLVS 200 signals which have not MIPI protocol?
Hard DPHY can only receive MIPI protocol. Hard D-PHY can not receive SLVS 200 signals which do not have MIPI protocol.