5879 - CrossLink: How to configure the Reference Design MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge for DSI single lane?<div><br></div>

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• 5775 - [CrossLink] [MIPI DSI Display Interface Bandwidth Reducer IP]:&nbsp;How many lanes can be set to configure the 1:2 MIPI DSI bandwidth reducer IP single lane?

  Please refer to the FPGA-IPUG-02028 document, otherwise known as 1:2 MIPI DSI Display Interface Bandwidth Reducer IP. Table 3.1 shows that the number of lanes is fixed to 4 and non-configurable.

• 6472 - Crosslink: Can I use FPGA chips of the CrossLink series to organize a bridge MIPI DSI to MIPI CSI-2?

  For your application needs, there is a Reference Design that you can try which is 1 to N MIPI CSI-2/DSI Duplicator. Please refer to the webpage and documentation is also provided: ...

• 5711 - FPDLink to DSI 1.2:&nbsp; OpenLDI to DSI IP seems to support on VESA mapping of the incoming OpenLDI datastream. Does this IP support the JEIDA mapping? In case it does not, how can we implement this functionality?

  The difference between VESA and JEIDA mapping looks like the arrangement of the sequence of signals. In the Verilog file generated under fdp_link_2_dsi which is located in the rtl folder, you may want to reconfigure the arrangement based on JEIDA ...

• 6140 - Crosslink: Is there any CSI-2 test pattern generator?

  In Crosslink IP, Lattice do not have color bar pattern generator except for cmos-to-dphy IP but you may try to check MIPI CSI-2 Transmit Bridge Reference Design for other Lattice FPGA devices. Here's the link: ...

• 7763 - I3C Controller IP - Where can I download the Out of the Box Design Example

  Please refer to below information: I3C IP User Guide : https://www.latticesemi.com/products/designsoftwareandip/intellectualproperty/ipcore/ipcores04/i3c-controller Navigate to the IPUG from the link: Documentation > Quick Reference > User Manual > ...