5636 - MachXO2/MachXO3 : Can I use XO2/XO3 to bridge multiple cameras?

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• 5485 - CrossLink: Why are there different clock frequencies when building a MIPI CSI-2 bridge?

  Description: It is easy to divide or multiple the clocks by power of 2. It is recommended to use divisible or factor by the multiples of 2 such as (2 and 4).

• 1000 - How can I implement multiple protocols within a PCS quad (Protocol A RX, Protocol B, TX, etc) on ECP2M and ECP3?

  For LatticeECP2M devices, all the four channels in a quad must be configured for the same protocol. In LatticeECP3 device family, multiple protocols within one quad of SERDES is supported. The standards are required to have the same reference clock ...

• 6472 - Crosslink: Can I use FPGA chips of the CrossLink series to organize a bridge MIPI DSI to MIPI CSI-2?

  For your application needs, there is a Reference Design that you can try which is 1 to N MIPI CSI-2/DSI Duplicator. Please refer to the webpage and documentation is also provided: ...

• 1873 - [LatticeECP3] Common Public Radio Interface - IP Core: Is the FIFO bridge in the PCS (Physical Coding Sub-layer) used in the low latency CPRI (Common Public Radio Interface) IP (Intellectual Property) core?

  LatticeECP3 supports CPRI (Common Public Radio Interface) low latency mode operation and the FIFO bridge in the SERDES/PCS is bypassed. The conditions are that the operation runs at full synchronous mode and data is handed off from SerDes/PCS to FPGA ...

• 4012 - [Lattice ECP3] PCI Express Endpoint Core IP: How does the Lattice PCIe (Peripheral Component Interconnect Express) IP core issue multiple MSI (Message Signaled Interrupts) when multiple MSI request bits are set in the end application?

  Description: The Lattice PCIe (Peripheral Component Interconnect Express) IP (Intellectual Property) core asserts all MSI one after the other. The Lattice PCIe (Peripheral Component Interconnect Express) IP (Intellectual Property) can handle up to 8 ...