5485 - CrossLink: Why are there different clock frequencies when building a MIPI CSI-2 bridge?

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• 6472 - Crosslink: Can I use FPGA chips of the CrossLink series to organize a bridge MIPI DSI to MIPI CSI-2?

  For your application needs, there is a Reference Design that you can try which is 1 to N MIPI CSI-2/DSI Duplicator. Please refer to the webpage and documentation is also provided: ...

• 6140 - Crosslink: Is there any CSI-2 test pattern generator?

  In Crosslink IP, Lattice do not have color bar pattern generator except for cmos-to-dphy IP but you may try to check MIPI CSI-2 Transmit Bridge Reference Design for other Lattice FPGA devices. Here's the link: ...

• 5813 - [CrossLink] For 2:1 MIPI CSI-2 Bridge Soft IP debugging, what caused hs_sync_ch0 unexpected behavior?

  The signals for sp_en is asserted every time there are frame start code, frame end code line start code and line end code through the data type. Line start and line end are optional as per CSI-2 specification v1.1. Thus, to enable in the testbench, ...

• 5777 - [CrossLink] [MIPI D-PHY to CMOS Interface Bridge IP]: What can be the cause of frequency calculation error in DPHY to CMOS GPLL after clicking the 'Calculate PLL Frequencies' button of the DPHY-to-CMOS v1.3 Clarity GUI with provided configuration

  With regards to D-PHY to CMOS v1.3 GUI, if the user happens to encounter the dialogue prompt saying that "the desired frequencies for this configuration could not be generated by the PLL", it means that it is not a recommended value that will be used ...

• 5636 - MachXO2/MachXO3 : Can I use XO2/XO3 to bridge multiple cameras?

  There are hardware limitations with XO2 and XO3 devices for this particular application. Please check our existing solution which is the "4 Input to 1 Output MIPI CSI-2 Camera Aggregator Bridge". It allows you to interface to multiple MIPI CSI-2 ...