6472 - Crosslink: Can I use FPGA chips of the CrossLink series to organize a bridge MIPI DSI to MIPI CSI-2?

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• 5879 - CrossLink: How to configure the Reference Design MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge for DSI single lane?<div><br></div>

  Please refer to FPGA-RD-02060 Section 3, Design and Module Description. On the project file, modify the rx_dphy which is declared under rx/rx.sbx. On the Receiver section of the IP, modify the RX Interface to DSI and the Number of RX Lanes to one.

• 6140 - Crosslink: Is there any CSI-2 test pattern generator?

  In Crosslink IP, Lattice do not have color bar pattern generator except for cmos-to-dphy IP but you may try to check MIPI CSI-2 Transmit Bridge Reference Design for other Lattice FPGA devices. Here's the link: ...

• 5775 - [CrossLink] [MIPI DSI Display Interface Bandwidth Reducer IP]:&nbsp;How many lanes can be set to configure the 1:2 MIPI DSI bandwidth reducer IP single lane?

  Please refer to the FPGA-IPUG-02028 document, otherwise known as 1:2 MIPI DSI Display Interface Bandwidth Reducer IP. Table 3.1 shows that the number of lanes is fixed to 4 and non-configurable.

• 5485 - CrossLink: Why are there different clock frequencies when building a MIPI CSI-2 bridge?

  Description: It is easy to divide or multiple the clocks by power of 2. It is recommended to use divisible or factor by the multiples of 2 such as (2 and 4).

• 5813 - [CrossLink] For 2:1 MIPI CSI-2 Bridge Soft IP debugging, what caused hs_sync_ch0 unexpected behavior?

  The signals for sp_en is asserted every time there are frame start code, frame end code line start code and line end code through the data type. Line start and line end are optional as per CSI-2 specification v1.1. Thus, to enable in the testbench, ...