5621 - Crosslink: Can Hard-DPHY receive SLVS 200 signals which have not MIPI protocol?
Hard DPHY can only receive MIPI protocol. Hard D-PHY can not receive SLVS 200 signals which do not have MIPI protocol.
Related Articles
6114 - Crosslink NX : Are there any Reference Designs of DPHY for different applications as stated below? 1. Connecting Soft DPHY Rx module output to Soft DPHY Tx module input. 2. Image acquisition from a camera through Hard DPHY.
Solution: The following RDs available for Crosslink-NX will support the said applications: 1. FPGA-RD-02212 : N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation - Aggregate multiple Image Sensors into a single Output with Minimal Latency. - Uses ...
5546 - <div>MachXO3: How to implement SLVS Rx (Receiver) IF (interface) in MachXO3 devices?</div>
Description: This article guides on implementing SLVS RX interface in MachXO3 devices. Solution: Since the 'IO_TYPE' cannot be set to "SLVS" in MachXO3, the LVDS25 buffer can be used to receive SLVS signals. This is because the 'differential input ...
6067 - [CrossLink-NX] MIPI: Why does MIPI CSI-2/DSI DPHY Transmitter IP working on Radiant 2.0 but not on latest version?
If Crosslink-NX device is an ES part, it is only supported by Lattice Radiant 2.0 SP1 Software.
5263 - CrossLink: In soft MIPI DPHY RX, should the clock be placed only on PCLK pins? and Can the clock also be placed on MIPI_CLK/GR_PCLK/GPLL pins?
The Clock should be placed only on PCLK pins and they cannot be placed on MIPI_CLK/GR_PCLK/GPLL pins. Only following pins may be used for MIPI CLK: PCLKC2_0, PCLKT2_0, PCLKC2_1, PCLKT2_1, PCLKC1_0, PCLKT1_0, PCLKC1_1 & PCLKT1_1. Also, The tool will ...
5578 - CrossLink: Can Hard D-PHY blocks be configured for more than 4 lanes?
Description: This FAQ explains why Hard D-PHY blocks cannot be configured for more than 4 lanes in CrossLink product. Solution: In CrossLink product, there are 2x 4-lane D-PHY. Each of the 4-lane D-PHY runs on its own clock and has its own clock ...