Details: 'Counter Width' refers to bus width of the counter that tracks the number of rows written during the high-speed data transition. Setting the value for Counter Width is valid only when RX_FIO type is set to 'QUEUE' where high-speed data is ...
Solution: The following RDs available for Crosslink-NX will support the said applications: 1. FPGA-RD-02212 : N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation - Aggregate multiple Image Sensors into a single Output with Minimal Latency. - Uses ...
Please refer to FPGA-RD-02060 Section 3, Design and Module Description. On the project file, modify the rx_dphy which is declared under rx/rx.sbx. On the Receiver section of the IP, modify the RX Interface to DSI and the Number of RX Lanes to one.
For your application needs, there is a Reference Design that you can try which is 1 to N MIPI CSI-2/DSI Duplicator. Please refer to the webpage and documentation is also provided: ...
In Crosslink IP, Lattice do not have color bar pattern generator except for cmos-to-dphy IP but you may try to check MIPI CSI-2 Transmit Bridge Reference Design for other Lattice FPGA devices. Here's the link: ...