6149 - Crosslink: In dphy_rx_wrap_beh.v, how do user resolve error related to port size mismatch?

• Related Articles

• 6114 - Crosslink NX : Are there any Reference Designs of DPHY for different applications as stated below? 1. Connecting Soft DPHY Rx module output to Soft DPHY Tx module input. 2. Image acquisition from a camera through Hard DPHY.

  Solution: The following RDs available for Crosslink-NX will support the said applications: 1. FPGA-RD-02212 : N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation - Aggregate multiple Image Sensors into a single Output with Minimal Latency. - Uses ...

• 7265 - MIPI CSI-2 / DSI D-PHY Transmitter: What is 'Counter Width' parameter in rx_dphy IP and how to calculate the value?

  Details: 'Counter Width' refers to bus width of the counter that tracks the number of rows written during the high-speed data transition. Setting the value for Counter Width is valid only when RX_FIO type is set to 'QUEUE' where high-speed data is ...

• 5924 - D-PHY to CMOS v1.2/CrossLink: Why does the DPHY RX channel signal did not move from LP to HS mode?

  This is due to metastability encountered in v1.2. It is recommended to upgrade to DPHY to CMOS v1.3 with the corresponding IP fix.

• 6140 - Crosslink: Is there any CSI-2 test pattern generator?

  In Crosslink IP, Lattice do not have color bar pattern generator except for cmos-to-dphy IP but you may try to check MIPI CSI-2 Transmit Bridge Reference Design for other Lattice FPGA devices. Here's the link: ...

• 5263 - CrossLink: In soft MIPI DPHY RX, should the clock be placed only on PCLK pins? and Can the clock also be placed on MIPI_CLK/GR_PCLK/GPLL pins?

  The Clock should be placed only on PCLK pins and they cannot be placed on MIPI_CLK/GR_PCLK/GPLL pins. Only following pins may be used for MIPI CLK: PCLKC2_0, PCLKT2_0, PCLKC2_1, PCLKT2_1, PCLKC1_0, PCLKT1_0, PCLKC1_1 & PCLKT1_1. Also, The tool will ...