5892 - CrossLink: new CSI-2/DSI DPY Receiver IP version v1.3, however why I have many unconstrained input_setup paths and how can to avoid this?

• Related Articles

• 6140 - Crosslink: Is there any CSI-2 test pattern generator?

  In Crosslink IP, Lattice do not have color bar pattern generator except for cmos-to-dphy IP but you may try to check MIPI CSI-2 Transmit Bridge Reference Design for other Lattice FPGA devices. Here's the link: ...

• 5775 - [CrossLink] [MIPI DSI Display Interface Bandwidth Reducer IP]: How many lanes can be set to configure the 1:2 MIPI DSI bandwidth reducer IP single lane?

  Please refer to the FPGA-IPUG-02028 document, otherwise known as 1:2 MIPI DSI Display Interface Bandwidth Reducer IP. Table 3.1 shows that the number of lanes is fixed to 4 and non-configurable.

• 5879 - CrossLink: How to configure the Reference Design MIPI DSI/CSI-2 to OpenLDI LVDS Interface Bridge for DSI single lane?<div><br></div>

  Please refer to FPGA-RD-02060 Section 3, Design and Module Description. On the project file, modify the rx_dphy which is declared under rx/rx.sbx. On the Receiver section of the IP, modify the RX Interface to DSI and the Number of RX Lanes to one.

• 5389 - CrossLink: Why does the generated VHDL code does not contain any ports for CSI2/DSI D-Phy Receiver IP?

  Description: CSI2/DSI D-Phy is a submodule IP. This only provides an instantiation templates for vhdl because it is expected that it will be used in a larger design. In addition, generating this IP is done in Verilog.

• 6067 - [CrossLink-NX] MIPI: Why does MIPI CSI-2/DSI DPHY Transmitter IP working on Radiant 2.0 but not on latest version?

  If Crosslink-NX device is an ES part, it is only supported by Lattice Radiant 2.0 SP1 Software.