Synthesis Inquiry / Failure
7769 - Radiant / System Verilog: How to fix the package not found issue for SystemVerilog to avoid synthesis failure?
Background: 'Package not found' synthesis issue is due to limitation of Radiant to automatically compile RTL files based on its expected arrangement. Solution: Here is the set of instructions to properly compile System Verilog RTL files: 1. In your ...
7735 - Radiant 2024.2 and Diamond 3.14 Synplify Pro: BN161: Net has multiple drivers warning
Description: Users may encounter the BN161: Net has multiple drivers warning when using Synplify Pro on Radiant 2024.2 and Diamond 3.14, even if their design has no multiple drivers. Solution: This is a known issue. Rest assured that this warning is ...
7713 - Radiant Synthesis with Synplify Pro: results differ on multiple machines
Description: When using Synplify Pro on different machines, the system environment could cause different behavior. Some symptoms of this issue include the following: 1. The synthesis behavior is different on another machine (e.g. passes or fails on a ...
7562 - Radiant: The synthesis design process does not complete when synthesis is run on Synplify Pro OEM
In Radiant, the synthesis and post-synthesis processes are a combined process under "Synthesize Design". When you run synthesis using the standalone version of Synplify Pro, this version generates a .vm file which will be used to run post-synthesis ...
7511 - Radiant: How to change the SynplifyPro version used in the tool?
There are two ways users can switch to a different SynplifyPro version other than Lattice Radiant OEM. Option 1: Setting Radiant GUI settings. 1. Open Radiant GUI. 2. Click Tools > Option 3. Under the General Tab, go to Directories 4. Uncheck the Use ...
7503 - All Lattice Software: Does all Lattice HDL Development Software support Matlab HDL Coder-generated HDLs?
The HDL Generated from the Matlab environment (Matlab HDL Coder) should be compatible with the HDL design development on Lattice FPGA. The HDL files generated from the HDL Coder are generic and FPGA synthesizable. Generally, it does not have a ...
7472 - Diamond 3.13 and below: warning occurs when generating VHDL simulation file WARNING - Duplicate names of DEFAULT at hierarchy level (-1) for type (Keyword) exist in the source design. Any names following the first will be uniquified.
Description: When generating a post-synthesis VHDL simulation file in Diamond, the warning below will occur: "WARNING - Duplicate names of DEFAULT at hierarchy level (-1) for type (Keyword) exist in the source design. Any names following the first ...
7425 - Radiant: How to use Synplify Pro on one file, and LSE on another in the same design?
The user has two options, they can use either Structural Design Flow or Block Based Design. The user can create a .vm (Structural) or .ipm (Block Based) file for one synthesis tool, and then instantiate it on another design with a different Synthesis ...
1149 - Diamond: Why does the user get warnings in the automake.log file regarding "Combinational Loops found"?
Use of combinational loops has long been discouraged because they can cause significant stability and reliability problems in a design. The combinational loop behavior is usually dependent on the relative propagation delays of the loop's logic. ...
2348 - Why is the shift register in my design implemented with the distributed RAM instead of register resources?
During synthesis Synplify will optimize the shift register into a distributed RAM implementation to save register resources if the shift register is wide and deep. The disadvantage of this implementation is that the shift register will be adversely ...
2345 - Lattice Mico: In a Mico System Builder(MSB) project, can the characters transmitted through the UART be displayed on the Simulator console?
Description: Yes. The characters transmitted through the UART can be displayed on the Simulator console window during simulation. To enable this: double click the UART component in the hardware platform of MSB on the 'transmit Settings for RTL ...
1148 - Lattice ispLEVER: Synthesis: Why run mixed language synthesis in ispLEVER 7.1 SP1 or 8.0 or 8.0 SP1 is not allowed?
Lattice ispLEVER: Synthesis: You can use a mixed language design which contains both VHDL and Verilog modules when using ispLEVER 7.1 SP1 (or 8.0 or 8.0 SP1). If you get an error message when the design is run then you need to adjust a setting in the ...
6938 - How to avoid the resource get optimized during Synthesis?
This is due to the optimization in the design during MAP. To avoid optimization during MAP, use syn_hier in the block level (submodules) and syn_keep + NOCLIP to the instance component at the top level file. Example: 1. Insert the attribute /* ...
1060 - How can I avoid the Lattice Radiant/Diamond to implement a 3-stage shift register as RAM-based shift register?
Description: Lattice Radiant / Diamond software tools will implement the following verilog code as RAM-based shift register instead of keeping the shift components as register. reg [6:0] shft_reg1, shft_reg2, shft_reg3; always @(posedge pclk) begin ...
5284 - iCECube2: How to change Synthesis engine in iCECube2?
To change synthesis engine in iCECube2, right click on "Synthesis Tool" (In the pane to the left side) then on "Select Synthesis tool" and choose the synthesis tool as per your requirement.
2290 - MachXO: How can I generate VME with Turbo mode in command line ?
Description: In Lattice ispVM System, you can generate this VME file in the following steps: Create a device list Select Turbo in Project Settings Dialog Box Save the configuration file XCF file Open a Command Prompt Window, change the current ...
1048 - Lattice Diamond: Synthesis: Synplify Pro: How to change the type of memory resources Synplify Pro uses when using inferred memory in HDL code?
Lattice Diamond: Synthesis: Synplify Pro: In many cases HDL code that infers a memory is implemented as EBR-based memory. This can cause issues for a customer who needs to be able to reset this memory to zero during operation. The Synplify compiler ...
6832 - Radiant / Diamond: Why does max fanout limit in the Synthesis Design Strategy setting not working on reset/clock net?
The maximum fanout in Synthesis Design Strategy is only followed by the logic in the design wherein clock and reset nets are excluded or does not strictly following it. To add fanout limit specific on reset and clock nets, use the attribute below: ...
2238 - LatticeECP2/M, ECP3: LatticeMico System provides an option to clone a platform. When should I use this feature?
Description: LatticeMico System provides a framework for connecting a LaticeMico32 or LatticeMico8 processor to a set of peripherals. The number of peripherals and the complexity of the connections can vary dramatically. Each LatticeMico System ...
1037 - LatticeMico32: Why does my LatticeMico32 debug session fail to launch?
Description: A common problem when trying to debug a LatticeMico32 C/C++ project is an error message that reads: "Check that the target FPGA contains an LM32 CPU with DEBUG_ENABLED equal to TRUE and that the FPGA has configured correctly." This error ...
2220 - LatticeECP2/ECP3: What does the LatticeMico8 linker error message "lm8-elf/bin/ld: region text is full (C_code.elf section .text)" mean?
Description: The text region of the .elf generated by the LatticeMico8 compiler refers to the instruction opcodes in the C/C++ source code and will be stored in the PROM memory of the LatticeMico8 controller. When these opcodes generated exceed the ...
2219 - LatticeECP2/ECP3: What does the LatticeMico8 linker error message "lm8-elf/bin/ld: region data is full (C_code.elf section .irq_stack)" mean?
The data region of the .elf generated by the LatticeMico8 compiler refers to the initialized and uninitialized data in the C/C++ source code and will be stored in the scratchpad memory of the LatticeMico8 controller. When this data generated exceeds ...
2214 - Diamond: What is the procedure to prevent unused IO logic from getting optimized out during Synthesis and MAP in Lattice Diamond, while using GUI or Active-HDL batch mode?
Lattice Diamond tool prevents unused, unconnected IO logic from getting generated, but sometimes user might want to keep a particular IO assignment and the related logic. Below is the procedure to prevent unwanted optimization: add the following ...
1029 - LatticeMico32: How do I use LatticeMico32 System Builder with multiple Cygwin installations?
Description: LatticeMico32 System Builder uses the Cygwin toolset as a basic foundation for the GNU C Compliler tools. Many other tool vendors also use the Cygwin system. However, each tool vendor may not be using the same version of Cygwin, and in ...
1027 - LatticeMico32: When I launch LatticeMico32 System Builder I'm asked to provide a location for the workspace. What is the workspace and how do I use it in Mico System Builder?
Description: The LatticeMico32 microprocessor development environment is based on the industry standard Eclipse Integrated Development Environment. The Eclipse development environment creates and uses a workspace file. The workspace is a source of ...
2153 - ispLEVER to Diamond: error generated when migrating a schematic-based design?
Description: The normal procedure to migrate a design to Lattice Diamond is by using the “Import ispLEVER Project..” option in the Lattice Design software. While importing, when you check “Copy design source to Implementation’s Source Directory”, all ...
4347 - ispLEVER Classic v1.8: Does the software support Mixed Verilog/VHDL as described in the ispLEVER Classic Installation Guide?
Solution: Classic does not support a mixed language project. Note that when you create a project, you have to choose a project type. Mixed language is not one of these. ispLEVER and Diamond do support mixed language but not Classic. The workaround is ...
2128 - Diamond / Synplify Pro: Does the warning "@W:MT246 Blackbox EHXPLLJ is missing a user supplied timing model" have any negative effect on the timing analysis and optimization, or the Quality of Results?
Description: In Diamond and when using Synplify Pro as the synthesis tool, this warning "@W:MT246 Blackbox EHXPLLJ is missing a user supplied timing model" can occur when performing synthesis with an instantiation of any IP core using IPexpress. ...
3991 - Lattice Diamond v3.1: How to set the behavior of unused pins in an FPGA design?
Solution: These are some of the workarounds: 1) In RTL code, assign the following attributes to the unused input: /* synthesis syn_force_pads=1 syn_noprune = 1 */ The 'syn_noprune' will not allow Synplify Pro to optimize unconnected I/O buffers and ...
3879 - Diamond 3.1: Why does the software shows compile issues when multidimensional arrays are packed?
Solution: If you use Synplify Pro, check the Verilog standard used by the tool. To check the Verilog standard: 1. Open Lattice Diamond project. 2. Go to Strategy->Synplify Pro->Verilog Input. Verilog 2001 standard does not support multidimensional ...
788 - Synplify Pro Standalone: Why the Lattice version of Synplify Pro NOT ALLOW to run the Synplify.exe or Synplify_pro.exe programs from the command line?
Synplify Pro Standalone: The Lattice OEM licence of Synplify Pro does not support running the Synplify.exe or Synplify_pro.exe programs from the command line. You will need to use the Synpwrap.exe program instead. Below is a command line example of ...
3853 - Diamond / All FPGA: How to make Synplify Pro use Embedded Block RAM (EBR) for the inferred ROM in my design?
Solution: To make Synplify Pro use EBR for the inferred ROM, use the attribute syn_romstyle with the value block_rom. Synplify Pro infers ROM only when the address width is more than 3. The usage of this attribute is the following: Verilog Syntax ...
775 - Diamond: How do I setup my favorite synthesis and simulation tools?
Description: Diamond tools come packaged with Synopsys's Synplify Pro synthesis tool (Lattice Device version) and Aldec's Active-HDL (Lattice Edition) simulation environment. In addition to these bundled tools, Diamond supports other synthesis and ...
3800 - Diamond: How to prevent the synthesizer from optimizing away any unused I/Os, and still like to have the unused I/Os as placeholder in the design?
Description: Nets and wires that are not driven will be optimized by the tool to reduce the number of resources during synthesis. In order to place it even if the nets and wires are not driven by any load, attributes syn_keep/noclio, and ...
736 - Lattice ispLEVER: Synthesis: Synplify Pro: How do I use Synplify PRO to view a schematic representation of the RTL in my project?
Lattice ispLEVER: Synthesis: Synplify Pro: To view the schematic representation of the RTL in your project in ispLEVER, do the following: Do a BUILD DATABASE Select TOOLS, SYNPLIFY PRO SYNTHESIS Select HDL-Analyst Select RTL, HIERARCHICAL VIEW (or) ...
735 - Lattice Diamond: Synthesis: Synplify Pro: How can I make Synplify Pro infer registers instead of RAM?
Lattice Diamond: Synthesis: Synplify Pro: There might be situations where you have written Verilog or VHDL code which infers a memory. However the design tools are implementing this as distributed RAM, which can't be initialized or preset to zero. ...
3782 - Diamond: How to use the <font face="Verdana">IEEE_PROPOSED library in my VHDL code in Synplify Pro?
The Synplify Pro that comes with Diamond does not support IEEE_PROPOSED Library explicitly, as all the packages of IEEE_PROPOSED are now implemented in IEEE Library only. To enable the IEEE_PROPOSED library packages for a design, follow these steps: ...
1839 - Synplify Pro: What is the SAFE attribute?
Synplify Pro has a special encoding directive, “safe”, that will add logic such that if the state machine ever reaches an invalid state, it will be forced to the reset state. This behavior has the advantage of avoiding any possible “hang” conditions, ...
712 - ispLEVER Classic: What are the things that can prevent ispLEVER Starter from installing correctly?
Solution: Due to the differences in hardware and software, there are differing reasons why the Lattice ispLEVER Starter software may have problems installing. Below is a list of things to check and try when diagnosing an ispLEVER installation ...
3671 - Diamond: Is there a need to run the complete implementation flow>to view the physical and floor plan views even there is small change in the design?
Solution: Yes, there is, even if a small modification happens in source code whether its a logic change or a code clean up, the Lattice Diamond considers them as a source code change and will run the complete implementation flow to view the Floor ...
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