Lattice ispLEVER: Synthesis: Synplify Pro: To view the schematic representation of the RTL in your project in ispLEVER, do the following:

1. Do a BUILD DATABASE
2. Select TOOLS, SYNPLIFY PRO SYNTHESIS
3. Select HDL-Analyst
4. Select RTL, HIERARCHICAL VIEW (or)
5. Select TECHNOLOGY, HIERARCHICAL VIEW

You should now see the schematic representation of the RTL in your project.

Additional information from the Synplify PRO help docs:

Hierarchical view: A Hierarchical view provides a high-level, technology-independent, graphic representation of your design after compilation, using technology-independent components like variable-width adders, registers, large multiplexers, and state machines.

RTL views correspond to the .srs netlist files generated during compilation. RTL views are only available after your design has been successfully compiled.

Technology View: A Technology view provides a low-level, technology-specific view of your design after mapping, using components such as look-up tables, cascade and carry chains, multiplexers, and flip-flops. Technology views are only available after your design has been synthesized (compiled and mapped).

To see the RTL schematic views in versions prior to ispLEVER 7.1, you can start up the Synplify software then:

1. Import the design into Synplify (ispLEVER project settings are not imported)
2. Push RUN
3. Select HDL-Analyst
4. Select RTL, HIERARCHICAL VIEW (or)
5. Select TECHNOLOGY, HIERARCHICAL VIEW