How to solve POSTSYN SynplifyPro error - " instantiating unknown module" "Failed to elaborate" ?

How to solve POSTSYN SynplifyPro error - " instantiating unknown module" "Failed to elaborate" ?

The SynplifyPro used in the Lattice Software is unable to optimize undeclared ports on the IP/primitive component.
The user has to declare those unused ports then they could left it open.

Verilog example: 
dc_ip adc_inst(
.adc_en_i(adc_en_r),
        .adc_resetn_i(adc_rst_n),
        .adc_clk_i(adc_clk_w),
        .fab_clk_i(fab_clk_w),
        .adc_cal_i(adc_start_cal_r),
        .adc_soc_i(adc_soc_r),
        .adc_calrdy_o(adc_calrdy_o),
        .adc0_ch_sel_i(adc0_ch_sel_r),
        .adc1_ch_sel_i(adc1_ch_sel_r),
        .adc_cog_o(adc_cog_w),
        .adc_eoc_o(adc_eoc_w),
        .adc_convstop_i(adc_convstop_i),
        .adc0_o(adc0_out_w),
        .adc1_o(adc1_out_w),
        .ADC_DN0(ADC_DN0),
        .ADC_DP0(ADC_DP0),
        .ADC_DN1(ADC_DN1), //unused port
        .ADC_DP1()); //unused port

VHDL example:
adc_inst: dc_ip 
port map(
adc_en_i => adc_en_i,
adc_resetn_i => adc_resetn_i,
adc_clk_i => adc_clk,
fab_clk_i => fab_clk,
adc_cal_i => adc_cal_i,
adc_soc_i => adc_soc_i,
adc_calrdy_o => adc_calrdy_o,
adc0_ch_sel_i => "0000",
adc1_ch_sel_i => "0000",
adc_cog_o => adc_cog_o,
adc_eoc_o => adc_eoc_o,
adc_convstop_i => adc_convstop_i,
adc0_o => adc0_o,
adc1_o => adc1_o
       ADC_DN0=> ADC_DN0,
       ADC_DP0=> ADC_DP0,
       ADC_DN1=> open, --unused port
       ADC_DP1=> open ); --unused port