2165 - Simulation: Steps to compile/elaborate a SERDES based design in NC-Verilog?

• Related Articles

• 7286 - Verilog Compiler Simulator (VCS) simulation: Error-[URMI] Unresolved modules

  Description: In VCS, an error can occur when simulating designs with some foundational IPs. Solution: This is due to the 'include lines in the Verilog files used for the IP/s. Thus, VCS cannot resolve these modules. See the following steps to be able ...

• Radiant / Third-Party Simulation Tools: How to simulate a PLL IP thru cmpl_libs in Synopsys VCS or Cadence Xcelium?

  Description: This example demonstrates the recommended procedure for simulating a phase-locked loop (PLL) IP, specifically a foundation IP, on the Avant-G70 device using the cmpl_libs method within Synopsys VCS or Cadence Xcelium. The cmpl_libs ...

• 6171 - Are Cadence NC-Sim and Xcelium supported in Diamond?

  For simulation, Lattice supports Cadence NC-Sim. Please see the additional notes below. Simulation libraries follow the Verilog/VHDL LRM, so moving from older to newer simulators should not be an issue. Moving from newer to older simulators may cause ...

• 7019 - OEM Modelsim: Fatal: (vsim-3693) The minimum time resolution limit (10fs) in the Verilog source is smaller than the one chosen for SystemC or VHDL units in the design. Use the vsim -t option to specify the desired resolution.

  Description: When running simulation wizard directly on a design which includes a PLL, a fatal error is encountered as given below ** Fatal: (vsim-3693) The minimum time resolution limit (10fs) in the Verilog source is smaller than the one chosen for ...

• 2552 - Diamond: What is Timing Simulation and what files does Lattice Diamond design generate to facilitate timing simulation.

  Solution: The Timing Simulation (unlike Functional Simulation or Static Timing Analysis) is the closest emulation of a actually downloaded design to a device. A step ahead of functional simulation where only RTL code is required to verify the ...