Radiant / Third-Party Simulation Tools: How to simulate a PLL IP thru cmpl_libs in Synopsys VCS or Cadence Xcelium?

Radiant / Third-Party Simulation Tools: How to simulate a PLL IP thru cmpl_libs in Synopsys VCS or Cadence Xcelium?

Description:
This example demonstrates the recommended procedure for simulating a phase-locked loop (PLL) IP, specifically a foundation IP, on the Avant-G70 device using the cmpl_libs method within Synopsys VCS or Cadence Xcelium. The cmpl_libs approach enables users to reference a precompiled device library from the Lattice Radiant software, eliminating the need to recompile the library during each simulation run. This significantly improves simulation efficiency by avoiding redundant compilation steps. Compared to manually specifying the device library path in every VCS or XRUN invocation, this method offers a more streamlined and time-saving workflow. The following steps outline the procedure for setting up and executing the simulation using this method.

Step Procedure for VCS:
Step 1: Setting of Environment Variables (may be optional to many users): To properly configure the VCS simulation tool, users must define specific environment variables that indicate the VCS installation directory and its required license. If these environment variables are already preconfigured in the user's system environment, this setup step can be omitted.

  1. $ setenv VCS_HOME <vcs_installation>/synopsys/VCS/<version> && setenv PATH $VCS_HOME/bin:$PATH

  2. $ setenv LM_LICENSE_FILE <port_name>@<server_name>

Step 2: Opening of Radiant Console, Library Compilation, and IP Generation from Foundation IP: To compile a targeted FPGA device library using Lattice Radiant and proceed with IP installation, users must first execute the cmpl_libs utility, specifying both the simulation vendor (e.g., Xcelium or VCS) and the corresponding FPGA device (e.g., Avant-G70). This step ensures that the simulation environment is correctly configured with the appropriate precompiled device models. Following this, users should navigate to the ip/ directory and run the ipgen command to initiate IP generation, which synthesizes the required IP cores based on the configuration files present in that directory.

  1. $ cd /home/jtoled/lscc/radiant/2025.1/bin/lin64

  2. $ ./radiantc

  3. $ cmpl_libs -sim_path <synopsys_installation_path>/synopsys/VCS/W-2024.09-1/bin -sim_vendor synopsys -device lav_atg -64 -target_path <user_defined_path>/vcs

  4. $ ipgen -o /home/jtoled/simulation/pll_avant/vcs/pll_avantIP -ip /home/jtoled/lscc/radiant/2025.1/ip/avant/pll_avant -name pll_avant0 -a LAV-AT -p LAV-AT-G70 -t LFG676 -sp 1 -op COM

  5. $ exit

      
Check the outputs and the logs produced after running the cmpl_libs. Take note that errors should be recorded in the logs.
                 

 Step 3: Copy the synopsys_sim.setup to the working simulation directory: When using the cmpl_libs utility with Synopsys VCS, the process generates a configuration file named synopsys_sim.setup. This file contains simulation setup directives, including references to precompiled device libraries and other simulation parameters. Users can modify this file to customize simulation behavior without needing to explicitly specify the device library path during each VCS invocation. The VCS tool is designed to automatically detect and load synopsys_sim.setup from the current working directory or predefined environment paths, streamlining the simulation setup process.

  1. $ cp /home/jtoled/simulation/compile_library/vcs/synopsys_sim.setup /home/jtoled/simulation/pll_avant/vcs

  2. $ cd /home/jtoled/simulation/pll_avant/vcs

            

Step 4: Run the vlogan and vcs commands: To compile and elaborate the design, users should first run vlogan to parse and compile the Verilog/SystemVerilog source files. Then, execute the vcs command to perform elaboration and generate simulation executables, including support for waveform dumping and debug capabilities.
      Step 4a.
  1.  vlogan -full64 -sverilog -timescale=1ns/1ps +libext+.v+.sv \

    -l /home/jtoled/simulation/pll_avant/vcs/pll_vcs_cmpl_lib.log \

    -work work \

    +incdir+/home/jtoled/simulation/pll_avant/vcs/pll_avantIP/testbench/ \

    /home/jtoled/simulation/pll_avant/vcs/pll_avantIP/rtl/pll_avant0.v \

    /home/jtoled/simulation/pll_avant/vcs/pll_avantIP/testbench/tb_top.v

      Step 4b.

  1. vcs -full64 -sverilog -debug_access+all -timescale=1ns/1ps \

    -o /home/jtoled/simulation/pll_avant/vcs/pll_vcs_simv \

    -l /home/jtoled/simulation/pll_avant/vcs/pll_vcs_sim.log \

    -top tb_top

      Resulting Logs


Step 5: Discovery Visualization Environment: Verify that the pll_vcs_simv simulation executable has been successfully generated, then launch it in GUI mode for waveform analysis and debugging.
  1.       $ pll_vcs_simv -gui
Resulting Waveforms



Step Procedure for Xcelium:
Step 1: Setting of Environment Variables (may be optional to many):  To properly configure the Xcelium  simulation tool, users must define specific environment variables that indicate the Xcelium installation directory and its required license. If these environment variables are already preconfigured in the user's system environment, this setup step can be omitted.

  1. $ setenv XCELIUM_HOME /tools/dist/cadence/XCELIUM/XCELIUM23.03.003/Linux/tools.lnx86 && setenv PATH $XCELIUM_HOME/bin:$PATH

  2. $ setenv LM_LICENSE_FILE <port_name>@<server_name>

Step 2: Opening of Radiant Console, Library Compilation, and IP Generation from Foundation IP: To compile a targeted FPGA device library using Lattice Radiant and proceed with IP installation, users must first execute the cmpl_libs utility, specifying both the simulation vendor (e.g., Xcelium or VCS) and the corresponding FPGA device (e.g., Avant-G70). This step ensures that the simulation environment is correctly configured with the appropriate precompiled device models. Following this, users should navigate to the ip/ directory and run the ipgen command to initiate IP generation, which synthesizes the required IP cores based on the configuration files present in that directory.

  1. $ cd /home/jtoled/lscc/radiant/2025.1/bin/lin64

  2. $ ./radiantc

  3. $ cmpl_libs -sim_path <cadence_installation_path>/XCELIUM/XCELIUM23.03.003/Linux/tools.lnx86/bin -sim_vendor cadence -device lav_atg -64 -target_path <user_defined_path>/xcelium 

  4. $ ipgen -o /home/jtoled/simulation/pll_avant/xcelium/pll_avantIP -ip /home/jtoled/lscc/radiant/2025.1/ip/avant/pll_avant -name pll_avant0 -a LAV-AT -p LAV-AT-G70 -t LFG676 -sp 1 -op COM

  5. $ exit

Check the outputs and the logs produced after running the cmpl_libs. Take note that errors should be recorded in the logs.
            
Step 3: Run the xrun command: To utilize the precompiled device library generated by cmpl_libs, users can run the xrun command with the -reflib option, which references the compiled library without requiring recompilation.

  1. $ xrun \

    -64bit -sv -access +rwc -timescale 1ns/1ps -libext .v,.sv \

    -l /home/jtoled/simulation/pll_avant/xcelium/pll0_xrun_reflib.log \

    -gui \

    -reflib /home/jtoled/simulation/compile_library/xcelium/lav_atg \

    -incdir /home/jtoled/simulation/pll_avant/xcelium/pll_avantIP/testbench \

    /home/jtoled/simulation/pll_avant/xcelium/pll_avantIP/rtl/pll_avant0.v \

    /home/jtoled/simulation/pll_avant/xcelium/pll_avantIP/testbench/tb_top.v

Step 4: Check for Errors: Ensure that the compilation and elaboration stages complete without errors by reviewing the terminal output for successful generation of the simulation executable and absence of fatal or syntax issues.
Resulting Logs

Step 5: SimVision and Console: Using the -gui option with the simulation command automatically launches SimVision along with its console interface, enabling interactive waveform viewing and debugging.
Resulting Waveforms