Radiant / Third-Party Simulation Tools: How to simulate a PLL IP thru manual library referencing in Synopsys VCS or Cadence Xcelium?

Description:

This example outlines a fallback simulation method for a Phase-Locked Loop IP on the MachXO5 device using Synopsys VCS or Cadence Xcelium. It involves manually referencing the Radiant device library using +incdir/-incdir (VCS/Xcelium) and -f. This will bypass the synopsys_sim.setup configuration in VCS. While less efficient than the cmpl_libs approach, this method remains valid and serves as interim guidance for VCS or Xcelium users pending official cmpl_libs support.

Step Procedure for VCS:

Step 1: Setting of Environment Variables (may be optional to many): To properly configure the VCS simulation tool, users must define specific environment variables that indicate the VCS installation directory and its required license. If these environment variables are already preconfigured in the user's system environment, this setup step can be omitted. Although the VCS_HOME AND LM_LICENSE_FILE are optional, for environment variable FOUNDRY, this is a mandatory requirement

1. $ setenv VCS_HOME <vcs_installation>/synopsys/VCS/<version> && setenv PATH $VCS_HOME/bin:$PATH
   

2. $ setenv LM_LICENSE_FILE <insert_your_license>
   

3. $ setenv FOUNDRY /home/jtoled/lscc/radiant/2025.1/ispfpga
   

Step 2: Opening of Radiant Console and IP Generation for Foundation IP:  To open and generate the PLL IP, the user should invoked the ipgen command tailored from the intended FPGA architecture and device inside the Radiant console.

1. $ cd <radiant_installation_path>/lscc/radiant/<version>/bin/lin64
   

2. $ ./radiantc
   

3. $ ipgen -o /home/jtoled/simulation/pll/vcs/pllIP -ip /home/jtoled/lscc/radiant/2025.1/ip/lifcl/pll -name pll0 -a LFMXO5 -p LFMXO5-25 -t BBG256 -sp 9_High-Performance_1.0V -op COM
   

4. $ exit
   

Step 3: Run the vcs command: The use of +incdir and -f options targeting the cae_library/ directory explicitly directs the compiler to include and process all primitive source files during simulation setup.

1. $ vcs  \

   -full64 -sverilog -debug_access+all -timescale=1ns/1ps +libext+.v+.sv \

   -o /home/jtoled/simulation/pll/vcs/pllIP/pll_simv \

   -l /home/jtoled/simulation/pll/vcs/pll0.log \

   +incdir+/home/jtoled/lscc/radiant/2025.1/cae_library/simulation/verilog/lfmxo5/ \

   +incdir+/home/jtoled/lscc/radiant/2025.1/cae_library/simulation/verilog/uaplatform/ \

   +incdir+/home/jtoled/lscc/radiant/2025.1/ip/pmi/ \

   -f /home/jtoled/lscc/radiant/2025.1/cae_library/simulation/verilog/lfmxo5/lfmxo5.f \

   -f /home/jtoled/lscc/radiant/2025.1/cae_library/simulation/verilog/uaplatform/uaplatform.f \

   -f /home/jtoled/lscc/radiant/2025.1/ip/pmi/pmi.f \

   +incdir+/home/jtoled/simulation/pll/vcs/pllIP/testbench/ \

   /home/jtoled/simulation/pll/vcs/pllIP/rtl/pll0.v \

   /home/jtoled/simulation/pll/vcs/pllIP/testbench/tb_top.v

Step 4: Discovery Visualization Environment: Verify that the pll_simv simulation executable has been successfully generated, then launch it in GUI mode for waveform analysis and debugging.

1. $pll_simv -gui

Resulting Waveform

Step Procedure for Xcelium:

Step 1: Setting of Environment Variables (may be optional to many): To properly configure the Xcelium  simulation tool, users must define specific environment variables that indicate the Xcelium installation directory and its required license. If these environment variables are already preconfigured in the user's system environment, this setup step can be omitted. Although the XCELIUM_HOME AND LM_LICENSE_FILE are optional, for environment variable FOUNDRY, this is a mandatory requirement

1. $ setenv XCELIUM_HOME <cadence_installation_PATH>/XCELIUM/XCELIUM23.03.003/Linux/tools.lnx86 && setenv PATH $XCELIUM_HOME/bin:$PATH
   

2. $ setenv LM_LICENSE_FILE <insert_your_license>
   

3. $ setenv FOUNDRY /home/jtoled/lscc/radiant/2025.1/ispfpga
   

Step 2: Opening of Radiant Console and IP Generation for Foundation IP: To open and generate the PLL IP, the user should invoked the ipgen command tailored from the intended FPGA architecture and device inside the Radiant console.

1. $ cd /home/jtoled/lscc/radiant/2025.1/bin/lin64
   

2. $ ./radiantc
   

3. $ ipgen -o /home/jtoled/simulation/pll/xcelium/pllIP -ip /home/jtoled/lscc/radiant/2025.1/ip/lifcl/pll -name pll0 -a LFMXO5 -p LFMXO5-25 -t BBG256 -sp 9_High-Performance_1.0V -op COM
   

4. $ exit
   

Step 3: Run the xrun command: The use of -incdir and -f options targeting the cae_library/ directory explicitly directs the compiler to include and process all primitive source files during simulation setup.

1. $ xrun \

   -64bit -sv -access +rwc -timescale 1ns/1ps -libext .v,.sv \

   -l /home/jtoled/simulation/pll/xcelium/pll0.log \

   -gui \

   -incdir /home/jtoled/lscc/radiant/2025.1/cae_library/simulation/verilog/lfmxo5/ \

   -incdir /home/jtoled/lscc/radiant/2025.1/cae_library/simulation/verilog/uaplatform/ \

   -incdir /home/jtoled/lscc/radiant/2025.1/ip/pmi/ \

   -f /home/jtoled/lscc/radiant/2025.1/cae_library/simulation/verilog/lfmxo5/lfmxo5.f \

   -f /home/jtoled/lscc/radiant/2025.1/cae_library/simulation/verilog/uaplatform/uaplatform.f \

   -f /home/jtoled/lscc/radiant/2025.1/ip/pmi/pmi.f \

   -incdir /home/jtoled/simulation/pll/xcelium/pllIP/testbench/ \

   /home/jtoled/simulation/pll/xcelium/pllIP/rtl/pll0.v \

   /home/jtoled/simulation/pll/xcelium/pllIP/testbench/tb_top.v

Step 4: SimVision and Console: Using the -gui option with the simulation command automatically launches SimVision along with its console interface, enabling interactive waveform viewing and debugging.

Resulting Waveform

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