Description: This FAQ complements Application Note FPGA-AN-02084 by offering practical guidance for using Synopsys VCS and Cadence Xcelium in Lattice FPGA simulations. It expands on the original note with real-world examples involving Lattice IPs and ...
Description: This example details the simulation flow for a PCIe server IP targeting the MachXO5 device using manual Radiant library references in VCS. or Xcelium The process includes configuring environment variables, generating the IP from the ...
Description: This example demonstrates the recommended procedure for simulating a phase-locked loop (PLL) IP, specifically a foundation IP, on the Avant-G70 device using the cmpl_libs method within Synopsys VCS or Cadence Xcelium. The cmpl_libs ...
Description: This example outlines a fallback simulation method for a Phase-Locked Loop IP on the MachXO5 device using Synopsys VCS or Cadence Xcelium. It involves manually referencing the Radiant device library using +incdir/-incdir (VCS/Xcelium) ...
The user has to compile both uaplatform and device (i.e., lfcpnx) libraries. uaplatform contains generic library functions like LUT4, BB, standard cell libraries etc and lfcpnx library contains device-specific libraries. While specific device library ...