Radiant / Third-Party Simulation Tools: How to simulate a PCIE IP in Synopsys VCS or Cadence Xcelium?

Description:

This example details the simulation flow for a PCIe server IP targeting the MachXO5 device using manual Radiant library references in VCS. or Xcelium The process includes configuring environment variables, generating the IP from the server repository, and executing simulation to produce waveform and debug data in GUI mode. A critical step involves installing the IP via the IP Catalog using TCL commands ip_catalog_list and ip_catalog_install.

Step Procedure for VCS:

Step 1: Setting of Environment Variables (may be optional to many): To properly configure the VCS simulation tool, users must define specific environment variables that indicate the VCS installation directory and its required license. If these environment variables are already preconfigured in the user's system environment, this setup step can be omitted. Although the VCS_HOME AND LM_LICENSE_FILE are optional, for environment variable FOUNDRY, this is a mandatory requirement

$ setenv VCS_HOME <vcs_installation>/synopsys/VCS/<version> && setenv PATH $VCS_HOME/bin:$PATH
$ setenv LM_LICENSE_FILE <insert_your_license>
$ setenv FOUNDRY /home/jtoled/lscc/radiant/2025.1/ispfpga

Step 2: Opening of Radiant Console, Server IP installation, and IP Installation and Generation from Server IP repository: To install the PCIe IP from the Server IP repository, execute ip_catalog_list and ip_catalog_install with the designated IP name and version within the radiantc console. Upon successful installation, the IP files are placed in the RadiantIPLocal/ directory, ready for generation targeting the intended FPGA architecture and device.

$ cd /home/jtoled/lscc/radiant/2025.1/bin/lin64
$ ./radiantc
$ ip_catalog_list -server
$ ip_catalog_install -vlnv latticesemi.com:ip:pcie_x4:3.5.1
$ ipgen -o /home/jtoled/simulation/pcie/vcs/pcieIP -ip /home/jtoled/RadiantIPLocal/latticesemi.com_ip_pcie_x4_3.5.1 -name pcie_ip0 -a LFMXO5 -p LFMXO5-55T -t BBG400 -sp 9_High-Performance_1.0V -op COM
$ exit

Step 3: Creation of pcie_files.f: This step involves creating a file list that specifies all required directories and source files for PCIe simulation. Although optional, it is strongly recommended to maintain a structured and readable simulation setup.

$ cd /home/jtoled/simulation/pcie/xcelium/pcieIP
$ nano pcie_files.f

Enter the list inside the pcie_files.f below then save and exit.

+incdir+/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/ \
+incdir+/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/testbench/ \
+incdir+/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/PCIE_DMA/ \
+incdir+/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/ \
+incdir+/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/DMA/ahb_arb/ \
+incdir+/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/DMA/apb_master/ \
+incdir+/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/DMA/debounce/ \
+incdir+/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/DMA/fifowrapper/ \
+incdir+/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/DMA/IP/ \
+incdir+/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/DMA/register_space/ \
+incdir+/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/DMA/sys_memory/ \
+incdir+/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/DMA/top/ \
/home/jtoled/simulation/pcie/vcs/pcieIP/rtl/pcie_ip0.sv
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/DMA/ahb_arb/ahb_arb.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/DMA/apb_master/apb_master.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/DMA/apb_master/apb_master_wrapper.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/DMA/apb_master/mux_synchronizer.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/DMA/debounce/debounce.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/DMA/fifowrapper/dpram_wrapper.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/DMA/fifowrapper/dpram_wrapper_256bits.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/DMA/fifowrapper/fifo_wrapper.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/DMA/IP/tdpram_sys_memory.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/DMA/IP/true_dp_ram.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/DMA/register_space/register_space.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/DMA/sys_memory/sys_mem.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/DMA/top/tb_dma_application_layer.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/apb_master_non_dma.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/apb_master_wrapper_non_dma.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/axi2tlp.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/debounce.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/depth2_fifo_new.sv
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/dma_fifo.sv
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/dma_flop_stg.sv
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/dma_rd_en_manager.sv
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/dma_rx_1_to_2_new.sv
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/dma_tx_2_to_1_new.sv
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/ep_mem_ram_128bit.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/ep_mem_ram_256bit.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/ep_mem_ram_32bit.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/ep_mem_ram_64bit.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/example_design_top.sv
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/LMMI_app.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/LMMI_app_LFCPNX.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/LMMI_app_LIFCL.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/pcie_app.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/pcie_app_32bit.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/pcie_ep_mem.sv
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/pcie_ep_mem_32bit.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/pcie_flopq.sv
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/pcie_rx_engine.sv
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/pcie_rx_engine_32bit.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/pcie_tx_engine.sv
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/pcie_tx_engine_32bit.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/pll_125.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/pll_250.sv
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/pll_62p5.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/pll_cnx.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/shreg_pipe_2stg.sv
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/shreg_pipe_ultimate.sv
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/tlp2axi.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/NON_DMA/ucfg_app.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/PCIE_DMA/aximm_dma_ed_top.sv
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/PCIE_DMA/axist_dma_ed_top.sv
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/PCIE_DMA/axist_generator.sv
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/PCIE_DMA/axi_mm_dma_ed_top_7s_LED_demo.sv
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/PCIE_DMA/debounce.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/PCIE_DMA/display_controller.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/PCIE_DMA/dma_flopq.sv
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/PCIE_DMA/dma_local_mem.sv
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/PCIE_DMA/LMMI_app.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/PCIE_DMA/pll_125.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/PCIE_DMA/pll_250.sv
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/PCIE_DMA/pll_250_and_7sclk.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/PCIE_DMA/pll_62p5.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/testbench/ahbl2tlp.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/testbench/apb4_master_bfm.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/testbench/axi2tlp.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/testbench/EXPRESSO_CORE0_APB_MASTER_regtest.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/testbench/EXPRESSO_CORE0_APB_MASTER_reg_lookup.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/testbench/EXPRESSO_CORE0_NWL_APB_MASTER_regtest.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/testbench/EXPRESSO_CORE0_NWL_APB_MASTER_reg_lookup.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/testbench/EXPRESSO_CORE1_APB_MASTER_regtest.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/testbench/EXPRESSO_CORE1_APB_MASTER_reg_lookup.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/testbench/EXPRESSO_CORE1_NWL_APB_MASTER_regtest.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/testbench/EXPRESSO_CORE1_NWL_APB_MASTER_reg_lookup.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/testbench/pcie_bfm_x4_4.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/testbench/pcie_model_x4_4.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/testbench/ref_design_ts.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/testbench/report_assertions_gen4.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/testbench/tb_top.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/testbench/test_defines.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/testbench/tlp2ahbl.v
/home/jtoled/simulation/pcie/vcs/pcieIP/testbench/testbench/tlp2axi.v

Step 4: Run the vcs command: The use of +incdir and -f options targeting the cae_library/ directory explicitly directs the compiler to include and process all primitive source files during simulation setup. This includes the pcie_files.f.

$ vcs -full64 -debug_access+all -sverilog -timescale=1ns/1ps \
+libext+.v +libext+.sv \
-o /home/jtoled/simulation/pcie/vcs/pcieIP/pcieIP_simv \
-l /home/jtoled/simulation/pcie/vcs/pcieIP/pcieIP.log \
+incdir+/home/jtoled/lscc/radiant/2025.1/cae_library/simulation/verilog/lfmxo5t/ \
+incdir+/home/jtoled/lscc/radiant/2025.1/cae_library/simulation/verilog/uaplatform/ \
+incdir+/home/jtoled/lscc/radiant/2025.1/ip/pmi/ \
-f /home/jtoled/lscc/radiant/2025.1/cae_library/simulation/verilog/lfmxo5t/lfmxo5t.f \
-f /home/jtoled/lscc/radiant/2025.1/cae_library/simulation/verilog/uaplatform/uaplatform.f \
-f /home/jtoled/lscc/radiant/2025.1/ip/pmi/pmi.f \
-f /home/jtoled/simulation/pcie/vcs/pcieIP/pcie_files.f \
-top tb_top

Step 5: Discovery Visualization Environment: Verify that the pcieIP_simv simulation executable has been successfully generated, then launch it in GUI mode for waveform analysis and debugging.

$ pcieIP_simv -gui

Resulting Waveform

Step Procedure for Xcelium:

Step 1: Setting of Environment Variables (may be optional to many): To properly configure the Xcelium simulation tool, users must define specific environment variables that indicate the Xcelium installation directory and its required license. If these environment variables are already preconfigured in the user's system environment, this setup step can be omitted. Although the XCELIUM_HOME AND LM_LICENSE_FILE are optional, for environment variable FOUNDRY, this is a mandatory requirement

$ setenv XCELIUM_HOME <cadence_installation_PATH>/XCELIUM/XCELIUM23.03.003/Linux/tools.lnx86 && setenv PATH $XCELIUM_HOME/bin:$PATH
$ setenv LM_LICENSE_FILE <insert_your_license>
$ setenv FOUNDRY /home/jtoled/lscc/radiant/2025.1/ispfpga

$ cd <radiant_installation_path>/lscc/radiant/<version>/bin/lin64
$ ./radiantc
$ ip_catalog_list -server
$ ip_catalog_install -vlnv latticesemi.com:ip:pcie_x4:3.5.1
$ ipgen -o /home/jtoled/simulation/pcie/xcelium/pcieIP -ip /home/jtoled/RadiantIPLocal/latticesemi.com_ip_pcie_x4_3.5.1 -name pcie_ip0 -a LFMXO5 -p LFMXO5-55T -t BBG400 -sp 9_High-Performance_1.0V -op COM
$ exit

$ cd /home/jtoled/simulation/pcie/xcelium/pcieIP
$ nano pcie_files.f

Note: Copy the lines listed from the section 'Creation of pcie_files.f' from VCS and replace the /vcs/ text with /xcelium/.

Step 4: Run the xrun command: The use of -incdir and -f options targeting the cae_library/ directory explicitly directs the compiler to include and process all primitive source files during simulation setup, including the pcie_files.f.

$ xrun \
-64bit -sv -access +rwc -timescale 1ns/1ps -libext .v,.sv \
-l /home/jtoled/simulation/pcie/xcelium/pcieIP/pcieIP.log \
-gui \
-ALLOWREDEFINITION \
-incdir /home/jtoled/lscc/radiant/2025.1/cae_library/simulation/verilog/lfmxo5t/ \
-incdir /home/jtoled/lscc/radiant/2025.1/cae_library/simulation/verilog/uaplatform/ \
-incdir /home/jtoled/lscc/radiant/2025.1/ip/pmi/ \
-f /home/jtoled/lscc/radiant/2025.1/cae_library/simulation/verilog/lfmxo5t/lfmxo5t.f \
-f /home/jtoled/lscc/radiant/2025.1/cae_library/simulation/verilog/uaplatform/uaplatform.f \
-f /home/jtoled/lscc/radiant/2025.1/ip/pmi/pmi.f \
-f /home/jtoled/simulation/pcie/xcelium/pcieIP/pcie_files.f \
-top tb_top

Note: -ALLOWREDEFINITION allows for recompilation and redefinition of modules, packages, and constructs that would normally cause compilation errors.

Step 5: SimVision and Console: Using the -gui option with the simulation command automatically launches SimVision along with its console interface, enabling interactive waveform viewing and debugging.

Resulting Waveform

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Radiant / Third-Party Simulation Tools: How to simulate a PCIE IP in Synopsys VCS or Cadence Xcelium?

Radiant / Third-Party Simulation Tools: How to simulate a PCIE IP in Synopsys VCS or Cadence Xcelium?

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