2552 - Diamond: What is Timing Simulation and what files does Lattice Diamond design generate to facilitate timing simulation.
Solution:
The Timing Simulation (unlike Functional Simulation or Static Timing Analysis) is the closest emulation of a actually downloaded design to a device. A step ahead of functional simulation where only RTL code is required to verify the behavior, the Timing Simulation takes into account all the gate delays of the device and helps the designer to emulate closest dynamic behavior of a digital design.
Because the total delay of a complete circuit depends on the number of gates a signal sees and how the gates have been placed and routed, you can only perform timing simulation after you have implemented the design.
Typically, to perform a timing simulation , you need two files which Lattice Design software will generate after implementation:
1. SDF
This is the Standard Delay Format file, which contain all the gate delay values, used to annotate timing values.
2. *.vo/*.vho files
This is the HDL file (Verilog /VHDL) for modelling physical netlist.
You can use the same test-bench that was used for functional simulation.
With these files, you can simulate the design after compiling them as usual.