Synplify Pro has a special encoding directive, “safe”, that will add logic such that if the state machine ever reaches an invalid state, it will be forced to the reset state. This behavior has the advantage of avoiding any possible “hang” conditions, where the state machine is unable to get back to a valid state while having minimal impact on the timing of the circuit.
VHDL Example
attribute syn_encoding of state : signal is "safe" ;
Verilog Example
reg [2:0] state; /* synthesis syn_encoding = "safe" */;