7472 - Diamond 3.13 and below: warning occurs when generating VHDL simulation file WARNING - Duplicate names of DEFAULT at hierarchy level (-1) for type (Keyword) exist in the source design. Any names following the first will be uniquified.

Description:
When generating a post-synthesis VHDL simulation file in Diamond, the warning below will occur:

"WARNING - Duplicate names of DEFAULT at hierarchy level (-1) for type (Keyword) exist in the source design. Any names following the first will be uniquified."

Solution:

This is a bug in Diamond 3.13 and below versions. Users can ignore these warnings since they would not have any impact on the VHDL output.

The fix will be implemented in future releases of Diamond.

Related Articles
1196 - Simulation: ALDEC Active-HDL: How to show signal hierarchy in the Active-HDL Waveform Editor? (I want to see the design hierarchy of a given signal.)<br>
Simulation: ALDEC Active-HDL: To see the design hierarchy for a given signal do the following: 1. Invoke the Active-HDL Waveform Editor. 2. Move your mouse over to the column header at the top of the Waveform Editor (e.g. "Name", "Value", etc). 3. ...
3845 - Diamond: How to create a VHDL output from a schematic file?
You can get a VHDL output from a schematic file by following these steps: 1. In project properties, change the Schematic HDL Type to VHDL. 2. Make any small changes in the schematic file and save it. 3. In the Hierarchy, get the VHDL source code for ...
Lattice Diamond: Why do i encounter a WARNING from my design relating to Diamond's Security feature? <div><br></div>
Description: When user design is compiled (Synthesis --> Bitstream) a Warning shown below is encountered WARNING -Security project file open Error! Security feature is turned OFF! Solution: The warning is valid and is just providing message that the ...
2385 - Modelsim:  After executing the orc_cmpl.bat ModelSim VHDL library compilation script, why do I get errors about unexpanded library elements when I compile my design?
The following online software documents explain how to compile the VHDL source library files for the stand-alone ModelSim flow: from the Lattice Diamond software tool: select Help-> Lattice Diamond Help. In the new pop-up web browser, select ...
ECP5 / Diamond 3.14: Why does my design get a Map device oversize error related to PLL for LFE5U-12F in with Diamond 3.14, but completes map successfully in earlier releases of Diamond software?
In Diamond version 3.14, there is a bug where it incorrectly limits the number of PLLs in the device to 0 for LFE5U-12F. Example error message: ERROR - (device oversize error). The number of PLL components needed (1) exceeds the number available. ...

7472 - Diamond 3.13 and below: warning occurs when generating VHDL simulation file WARNING - Duplicate names of DEFAULT at hierarchy level (-1) for type (Keyword) exist in the source design. Any names following the first will be uniquified.

7472 - Diamond 3.13 and below: warning occurs when generating VHDL simulation file WARNING - Duplicate names of DEFAULT at hierarchy level (-1) for type (Keyword) exist in the source design. Any names following the first will be uniquified.

Related Articles

1196 - Simulation: ALDEC Active-HDL: How to show signal hierarchy in the Active-HDL Waveform Editor? (I want to see the design hierarchy of a given signal.)<br>

3845 - Diamond: How to create a VHDL output from a schematic file?

Lattice Diamond: Why do i encounter a WARNING from my design relating to Diamond's Security feature?&nbsp;<div><br></div>

2385 - Modelsim:&nbsp; After executing the orc_cmpl.bat ModelSim VHDL&nbsp;library compilation script, why do I&nbsp;get errors about unexpanded library elements when I compile my design?

ECP5 / Diamond 3.14: Why does my design get a Map device oversize error related to PLL for LFE5U-12F in with Diamond 3.14, but completes map successfully in earlier releases of Diamond software?

Lattice Diamond: Why do i encounter a WARNING from my design relating to Diamond's Security feature? <div><br></div>

2385 - Modelsim: After executing the orc_cmpl.bat ModelSim VHDL library compilation script, why do I get errors about unexpanded library elements when I compile my design?