Use of combinational loops has long been discouraged because they can cause significant stability and reliability problems in a design. The combinational loop behavior is usually dependent on the relative propagation delays of the loop's logic.

Typically, combinational loops creep into a design to handle sticky asynchronous issues. A combinational loop is essentially the implementation of an implied or inferred latch. An inferred latch is an example of a combinational feedback loop because this function has to be built out of LUTs since there is no latch mode for the FPGA registers. When latches are implemented in LUTs, the timing analysis tool is not able to check the setup and hold time requirements on these circuits. Most design issues in which a combinational loop have been employed can be solved with a standard register, and the design will be more robust and stable.

Combinational loop warning are usually a result of "combinational" logic code that isn't strictly combinational. These Combinational loops are usually associated with an error in the "Case" structure or the "IF/Then/Else" structure. (e.g. An incompletely specified "case statement"). One suggestion is to keep registers in separate processes from combinatorial logic. This makes it easier to tell if the inferred latch is really an error.

Users should investigate any combinational loops and implement a fix to the RTL to remove unintended latches or redesign the circuit so that no latch is required.