Description:
Nets and wires that are not driven will be optimized by the tool to reduce the number of resources during synthesis. In order to place it even if the nets and wires are not driven by any load, attributes syn_keep/noclio, and syn_preserve/syn_force_pads are added in the RTL.
Solution:
To prevent the synthesizer from optimizing away unused I/Os in your design, use the attributes of Synplify Pro.
See the example code below.
Example:
1. Lattice Synthesis Engine (LSE)
a. Verilog
//************************************************************************************
module Dummy_IOs (dummy_in, dummy_out);
input [1:0] dummy_in;
output [1:0] dummy_out;
wire [1:0] dummy_signal_in /* synthesis syn_keep=1 */ /* synthesis NOCLIP="on"*/;
wire [1:0] dummy_signal_out /* synthesis syn_keep=1 */;
assign dummy_signal_in = dummy_in; //dummy statement for preserving inputs
assign dummy_out = dummy_signal_out; //dummy statement for preserving outputs
endmodule
//************************************************************************************
b. VHDL
--************************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity Dummy_IOs is
port
(
dummy_in : in std_logic_vector (1 downto 0);
dummy_out : out std_logic_vector (1 downto 0)
);
end Dummy_IOs;
architecture rtl of Dummy_IOs is
signal dummy_signal_in : std_logic_vector(1 downto 0);
signal dummy_signal_out : std_logic_vector(1 downto 0);
attribute syn_keep : boolean;
attribute noclip : string;
attribute noclip of dummy_signal_in : signal is "on";
attribute syn_keep of dummy_signal_in : signal is true;
attribute syn_keep of dummy_signal_out : signal is true;
begin
dummy_signal_in <= dummy_in; -- dummy statement for preserving inputs
dummy_out <= dummy_signal_out; -- dummy statement for preserving outputs
end rtl;
--************************************************************************************
2. Synplify Pro
a. Verilog
//************************************************************************************
module Dummy_IOs (dummy_pins) /* synthesis syn_force_pads=1 syn_noprune=1*/;
inout [3:0] dummy_pins;
wire dummy_signal;
assign dummy_signal = dummy_pins[0]; //dummy statement
endmodule
//************************************************************************************
b. VHDL
--************************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity Dummy_IOs is
port
(
dummy_pins : inout std_logic_vector(3 downto 0)
);
end Dummy_IOs;
architecture rtl of Dummy_IOs is
signal dummy_signal : std_logic;
attribute syn_noprune : boolean;
attribute syn_force_pads : boolean;
attribute syn_noprune of rtl : architecture is true;
attribute syn_force_pads of rtl : architecture is true;
begin
dummy_signal <= dummy_pins(0) ; -- dummy statement
end rtl;
--************************************************************************************