1148 - Lattice ispLEVER: Synthesis: Why run mixed language synthesis in ispLEVER 7.1 SP1 or 8.0 or 8.0 SP1 is not allowed?<br>
Lattice ispLEVER: Synthesis: You can use a mixed language design which contains both VHDL and Verilog modules when using ispLEVER 7.1 SP1 (or 8.0 or 8.0 SP1). If you get an error message when the design is run then you need to adjust a setting in the "Environment Options" dialog box. Please open the "Environment Options" dialog box and click on the "Directories" tab. Below the Synplify path there should be 2 check boxes; 1 labeled "SynplifyPro" and 1 labeled "OEM Tool". Please be sure that both of these check boxes are checked.
If only "OEM Tool" is checked then Project Navigator will open the OEM version of Synplify rather than SynplifyPro. The OEM version of Synplify does not support mixed language synthesis and this will produce an error message.
If only "SynplifyPro" is checked then the Project Navigator will look in the path for an non-OEM version of SynplifyPro and run this. If the path is pointing to the Lattice OEM version of SynplifyPro then it will appear to run the design but it will error out when trying to write the EDIF file. The error message, which is shown below, is not descriptive but the error is associated with a license error that prevents SynplifyPro from writing the EDIF file.
Error output EDIF file c:/datap/test_ecp2m/ecp2m_pll/count.edi
Error executing Synplicity VHDL/Verilog HDL Synthesizer with code 2
Done: failed with exit code: 0002.
Note: Beginning with ispLEVER 8.1, the version of Synplify was upgraded so that mixed language synthesis is supported by default and there is only one check box listed.