The maximum fanout in Synthesis Design Strategy is only followed by the logic in the design wherein clock and reset nets are excluded or does not strictly following it.
To add fanout limit specific on reset and clock nets, use the attribute below:
Attribute: syn_maxfan
Verilog Example
module test (registered_data_out, clock, data_in);
output [31:0] registered_data_out;
input clock;
input [31:0] data_in /* synthesis syn_maxfan=1000 */;
reg [31:0] registered_data_out /* synthesis syn_maxfan=1000 */;
VHDL Example
entity test is
port (clock : in bit;
data_in : in bit_vector(31 downto 0);
registered_data_out: out bit_vector(31 downto 0) );
attribute syn_maxfan : integer;
attribute syn_maxfan of data_in : signal is 1000;