1060 - How can I avoid the Lattice Radiant/Diamond to implement a 3-stage shift register as RAM-based shift register?
Description:
Lattice Radiant / Diamond software tools will implement the following verilog code as RAM-based shift register instead of keeping the shift components as register.
reg [6:0] shft_reg1, shft_reg2, shft_reg3;
always @(posedge pclk) begin
shft_reg1 <= din;
shft_reg2 <= shft_reg1;
shft_reg3 <= shft_reg2;
end
Solution:
As a workaround, user can try the following method:
-Method 1:
The Synthesis tool will determine whether to implement the sequential shift register as register, distribute-RAM or block RAM based on certain criteria. The user can choose a different implementation by specifying syn_ramstyle or syn_srlstyle attributes. The attributes can be applied globally, to a module or to a RAM instance. For examples:
module (...) /* synthesis syn_ramstyle="block_ram" */;
-Method 2:
reg [3:0] regBank[15:0] /* synthesis syn_srlstyle="registers" */;
For more details of the Syntax and attribute value, please refer to the online help Synplify reference manual.
-Method 3:
An alternative solution is to use syn_keep attribute to preserve those register signals. The Synplify will automatically implement the shift component as registers.