During synthesis Synplify will optimize the shift register into a distributed RAM implementation to save register resources if the shift register is wide and deep. The disadvantage of this implementation is that the shift register will be adversely effected in relation to the performance. If the performance has a higher priority than the area, you can prohibit the optimization by adding a Synplify attribute "syn_srlstyle = registers" for the shift register. For example,
In Verilog:
reg [15:0] a_reg /* synthesis syn_srlstyle="registers" */;
In VHDL:
signal a_reg : std_logic_vector(15 downto 0);
attribute syn_srlstyle : string;
attribute syn_srlstyle of a_reg : signal is "registers";
If there are a lot of big shift registers in your design, you have to add the attribute to each instantiation.
Another way is to add the attribute in the .sdc constraint file for the whole design. For example:
define_scope_collection foo {find * -hier -filter @kind==seqshift}
define_attribute {$foo} {syn_srlstyle} {registers}
When the "syn_srlstyle" attribute is set to "registers", Synplify will implement the shift register using register resources and not with the distributed RAM.