Place & Route (PAR) Inquiry / Failure
7739 - Radiant 2024.2 SP1: How can I resolve the PAR internal fatal error that only occurs on my design using Radiant 2024.2 SP1?
Description: In Radiant 2024.2 SP1, there is PAR internal fatal error occurs due to a crash on the STA. This error is not limited to a specific device. A symptom that the design is affected by this issue is if this design is passing PAR on older ...
5751 - Radiant 1.0 Service Pack 1: Why is there a fatal error when running PAR with the reference design named "Key Phrase Detection Using Compact CNN"?
Solution: This is a known issue in Radiant 1.0 Service Pack 1 and is documented in FPGA-RD-02033 page 4 section 3 Software Requirements.
6982 - Radiant: Why do we encounter the error: "PAR does not support signal <clock name> driving more than two DCCs"?
Solution: In Lattice Radiant software, the error "PAR does not support signal driving more than two DCC" is because PAR (Place and Route) only supports one or two DCC (Dynamic Clock Control) loads for one clock signal at present. The reason is, each ...
6850 - Diamond: ERROR - Based on the current IO attributes settings, port xxxxx cannot be assigned to pin [xx].
Description: This article explains an error in Diamond which reports the port cannot be assigned to certain pin during synthesis due to the pin assignment done via constraint. Solution: This error in Diamond is caused by optimization done during ...
5229 - CrossLink / DPHY to CMOS IP v1.2: Why am I not able to place the GPIO/IO_ports on bank0 in CrossLink while using DPHY to CMOS IP?
Description: When placing CMOS IO to Bank0, P&R errors are encountered indicating of wrong placement in the I/O bank0.
4529 - Diamond 3.5: Does recovery and removal timing analysis is performed on Flip-Flop when Infer GSR (Global Set/Reset) option is set to True in Strategy setting?
Solution: No, it does not. Recovery and removal timing analysis is performed in design if GSR-True in design. Timing analysis is not applied to any signal attached to the GSRN net on the devices. So if the reset on the device is routed via the GSRN ...
929 - Diamond: Place and Route: Timing: What is Auto hold-time correction setting in PAR?
Diamond: Place and Route: Timing: When the PAR (Place And Route) property auto hold-time correction is set to On, the router automatically inserts extra wires to compensate for the hold time violation on affected registers. Internal hold time ...
908 - Diamond: ECP2: How many generic routing signals can be used as primary clocks in a LatticeECP2/M device?
Diamond: ECP2: In a LatticeECP2/M, the primary clocks, whether they're global or quadrant, get their sources through a center MUX. The number of generic routing signals that can get onto the center MUX is 10. These 10 signals come from FPGA routing ...
2024 - LatticeECP3: How do I determine the delay of a LaticeECP3 DCS cell from a Place and Route TRACE Report?
A DCS (Dynamic Clock Select) element only drives primary clock nets. That is why the DCS cell delay is not presented by itself in a Place and Route TRACE Report. A TRACE report will show a 0 delay through the DCS cell. Instead, the sum of the DCS and ...
2011 - When executing multiple Place and Route (PAR) Jobs in parallel, what is the maximum number that can be executed at one time?
Running Multiple PAR jobs in parallel in Lattice Diamond is controlled using the multi-tasking node list option. Each PAR job must run on a separate CPU core. The node list file contains a "CORENUM" setting allowing the user to define the number of ...
900 - ispLEVER: Diamond: Place and Route: Suggestions and tips to place and route on a congested design?
ispLEVER: Diamond: Place and Route: As the designs get more complicated with multiple IPs, placing and routing of a design become a challenge for FPGAs. Here are some guidelines when handling a congested design. 1. Always use the latest software for ...
1915 - Diamond: ERROR - par: Failed to dump design to file.
The complete message for this error message is: ERROR - par: Failed to dump design to file <<FILE_PATH>/<FILE_NAME>.ncd> INTERNAL CODE : ncdesign:basncdesign:2244:2.13 In Diamond, when user performs PAR they might encounter this error message for ...
1907 - Diamond: Can user run multiple Place and Route (PAR) in parallel?
User can run multiple Place and Route (PAR) in parallel. This run method is effective when user have either a multicore machine, networked machine with access to other machine's resources, or both. A non-networked single core machine can not take ...
723 - Lattice Diamond: PAR: What's the best way to place and route a congested design?
Lattice Diamond: PAR: Here are some guidelines when handling a congested design. Always use the latest software for synthesis, map, and place and route. Both synthesis vendors and FPGA companies are constantly fine-tuning the tools to make them more ...
1829 - Diamond: How does multiple Place and Route assign jobs on Linux?
The multiple Place and Route tool in Diamond uses two different methods for assigning jobs. They are: bash rsh Jobs that are configured to be run on the local node are spawned using /bin/bash, with one place and route task assigned to one ...
1805 - Diamond: Can user make post Place and Route (PAR) changes to the design without having to run through the entire Lattice Diamond design flow?
Changes to the post PAR design are generally refereed to as Engineering Change Orders, or ECOs. The changes are directly written into the Native Circuit Description (.ncd) database file without requiring that user go through the entire design ...
1774 - Diamond: How can the user set the DELAYB cell to add delay to an input port when a single register exists between the input and output ports?
When only one register is present between the primary input and the primary output ports, that register is automatically placed in the output PIO cell . This prevents the DELAYB cell from being used in the input PIO cell even when user add the DELAYB ...
627 - Lattice Diamond: What is the PAR Strategy Auto Hold Time Correction used for?
Auto Hold-Time Correction controls whether the router will automatically insert extra wires to compensate for the hold time violation on affected registers. Auto hold-time correction has a negative impact on your setup time. If the setup time is more ...
6061 - CrossLink: Do we have layout recommendation and break out examples for the ckfBGA in FPGA-TN-02024?
In section 4.8 of FPGA-TN-02024, This breakout uses a LIF-MD6000 PLD in a 6.5 mm x 6.5 mm and 7.0 mm x 7.0 mm, and so on. The first is for ctfBGA while the latter is ckfBGA.
2831 - Lattice Diamond / ECP3: Why is software unable to complete PAR on the LVDS clock when utilizing general routing?
Description:An error message is received when routing with general routingERROR - par: netsanitycheck: the clock clk_lvds_rx_p_c on comp adcif_inst/Inst3_EHXPLLF port CLKI is driven by general routing through comp clk_lvds_rx_p. Please consult ...
2739 - Lattice Diamond: What are the Linux environment variables and their values needed to run Multiple PAR jobs in parallel?
After each node description as been defined in the node list file input, each node must contain an .rc file (.bashrc if the bash shell used) that runs automatically when a remote shell (rsh) call is received by that node. The environment variables ...
2612 - Why is some logic in a sub-module not packed into the group after Place and Route (PAR) when this sub-module is grouped with the HGROUP attribute in the source code?
Sometimes, Synplify will move some logic out of the sub-module for the optimization purpose by default. In order to avoid it, the syn_hier attribute should be added in the sub-module. The usage example is shown below: In Verilog, module dp(clk, rst, ...
217 - Diamond: Why does the design trigger warning messages stating Edge or Primary clock is un-routable, occupied and uses general routing, or are not placed on sweet site?
Occasionally in congested designs a conflict occurs resulting in an unroutable condition during the Place and Route (PAR) phase of a design. The conflict can be due to components that have been placed by user constraints, or by the decisions made by ...
2389 - Do BLOCK constraints limit the maximum coverage % reported in the timing report that can be achieved (<100%)?
The timing report generated by the Lattice Diamond Place and Route Tools report a timing coverage %. This number tells the user how complete their timing report is. Some customers require 100% timing coverage to ensure their designs are fully timed. ...
1289 - Lattice ispLEVER: Place and Route: Why do I get a warning message about an edge clock not on a sweet site during place and route when targeting an SC/M?
Lattice ispLEVER: Place and Route: In congested designs a conflict may occur resulting in an unroutable condition in PAR. This may be due to user constraints or unfavorable placement of logic by the software. Depending on the size and complexity of a ...
5699 - iCEcube2: This error appears: "I2712: Tool unable to find location for GB Error during global Buffer placement". How can this error be removed?
Description: The error is caused by Synplify Pro generating too many GB (Global Buffer). Solution: There are 2 solutions that will work as stated below: 1. The solution is to set the attribute below in your RTL: /* synthesis syn_global_buffers = */; ...
191 - ispLEVER Classic: What is the meaning of the ispLEVER Classic warning <warning>"P38088: Balanced partitioning turned off"?</warning>
This warning indicates that the balanced partitioning strategy of the fitter is turned off in order to find a successful fit for the design. Balanced partitioning is a method to keep the CPLD utilization uniform across the device. Therefore, if the ...
5569 - iCEcube2: How to use RGB pins of an ICE40 device as an input?
Description: In order to use the iCE40 open drain (RGB , IR) pins for general purpose functionality, you need to instantiate the SB_IO_OD primitive in the design. The details for the SB_IO_OD primitive can be found from the "iCE Technology library" ...
7281 - Radiant 2023.2 and above: Why does the command "-exp WARNING_ON_PCLKPLC1=1" on PAR does not work on Radiant 2023.2?
Description: In Radiant 2023.1 and lower versions, the command "-exp WARNING_ON_PCLKPLC1=1" works to bypass the DRC error when assigning clock ports on pins that are not PCLK. Due to some changes with the DRC of Radiant 2023.2, it also affected the ...
6838 - Radiant: How can users pack cells (LUTs or FFs) on specific slices in PAR?<input type="text" disabled class="wizardinput" style="border-right: none; border-left: none; padding-right: 0px; padding-left: 0px; opacity: 0.5; filter: grayscale(1); visibility: hidden; width: 1px;">
Users can use ldc_set_location constraints on a PDC file. See below: ldc_set_location -site {R5C5A} [get_cells {REG0.ff_inst GATE0 REG1.ff_inst GATE1}] ldc_set_location -site {R5C5B} [get_cells {REG2.ff_inst GATE2 REG3.ff_inst GATE3}] ...
6282 - Diamond: ERROR - par: I/O initial placement is unsuccessful. Check the I/O placement constraints / user preferences (such as pin locking) carefully
Description: When compiling a design on Diamond with multiple unassigned output ports, the below error might occur. "ERROR - par: I/O initial placement is unsuccessful. Check the I/O placement constraints / user preferences (such as pin locking) ...
6706 - Diamond 3.12: Is it normal for the placement and routing, and in turn, the generated bitstream, to change when a part of the RTL is changed, even if it wouldn't change the overall logic?
Solution: Yes. The software generates a new PAR seed every time a change is made to the design RTL, regardless of the change's impact on the overall logic of the design.
6659 - Diamond 3.12 and All FPGA: Is it normal for the placement and routing, and in turn, the generated bitstream, to change when a part of the RTL is changed, even if it wouldn't change the overall logic?
Description: Diamond software just checks ANY changes in the RTL for it to change its seed. Solution: Yes. The software generates a new PAR seed every time a change is made to the design RTL, regardless of the change's impact on the overall logic of ...
6645 - Radiant: Why PAR fails for some PCLK input ports for the Aligned DDR interface?
Aligned interfaces based on the FPGA-TN-02286: MachXO5-NX HighSpeed IO Interface technote should have DLLDELs connected to their CLKIN ports. Based on FPGA-DS-02102: MachXO5-NX Family datasheet, only even PCLKs are connected to DLLDELs. PCLK<Bank ...
6565 - Radiant: How to move a FF (register ) to IOB pins or move IOB to an internal register FF?
Description: The user can use the synthesis attribute syn_useioff to perform the two conditions: moving Register (FF) to IOB pins or move IOB to an internal Register (FF). Solution: Verilog example: module test (a, b, clk, rst, d) /* synthesis ...
7072 - Why there are designs passing on MAP showing a good SLICE utilization percentage but failing PAR showing unplaced SLICEs due to 100% SLICE utilization percentage?
To give a background on this, in a single SLICE, there can be two possible registers/FFs. Map does the SLICE utilization calculation solely based on the number of registers/FF per SLICE. Architecturally, there are 2 FFs/registers and 2 LUTs per ...
5984 - Lattice Diamond: Why do i encounter an error relating to the usage of the DELAYD primitive on my DDR Design? 
Description: When using the DELAYD primitive for MachXO2, there is an error message such as this: ERROR - Dynamic delay component 'delayd_0' cannot drive component 'Z_out_pad_RNO' Solution: According to the MachXO2/XO3 usage model, the dynamic delay ...