Radiant: Why PAR fails for some PCLK input ports for the Aligned DDR interface?

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• Radiant 2023.2 and above: Why does the command "-exp WARNING_ON_PCLKPLC1=1" on PAR does not work on Radiant 2023.2?

  Description: In Radiant 2023.1 and lower versions, the command "-exp WARNING_ON_PCLKPLC1=1" works to bypass the DRC error when assigning clock ports on pins that are not PCLK. Due to some changes with the DRC of Radiant 2023.2, it also affected the ...

• Radiant: How does the user set constraints for a MII interface?

  1. First step is to check the specs of the MII PHY. As an example, see analysis of the specs MII PHY together with what constraint would used the spec. ...

• 1774 - Diamond: How can the user set the DELAYB cell to add delay to an input port when a single register exists between the input and output ports?

  When only one register is present between the primary input and the primary output ports, that register is automatically placed in the output PIO cell . This prevents the DELAYB cell from being used in the input PIO cell even when user add the DELAYB ...

• 2997 - Lattice Diamond: How does the synthesis tool treat the unused input and output ports declared in the RTL code and not used(logic is not being assigned to the IO Ports)?

  The synthesis tool will remove the unused Input ports declared in the design. For unused Output ports, the tool can either tie them to the GND or leave them tri-stated. You can check this in the RTL view of the Synthesis tool. It is recommended to ...

• <div>Lattice Diamond: Why do i encounter an error relating to the usage of the DELAYD primitive on my DDR Design?&nbsp;</div>

  Description: When using the DELAYD primitive for MachXO2, there is an error message such as this: ERROR - Dynamic delay component 'delayd_0' cannot drive component 'Z_out_pad_RNO' Solution: According to the MachXO2/XO3 usage model, the dynamic delay ...