Radiant: How does the user set constraints for a MII interface?

Radiant: How does the user set constraints for a MII interface?


1. First step is to check the specs of the MII PHY.
As an example, see analysis of the specs MII PHY together with what constraint would used the spec.

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Regarding the specs of the MII PHY, see comments/notes on how to use them for the constraints:
1. Tclkp (Period): User could set this using create_clock or create_generated clock constraints
2. Tclkh and Tclkl (High time and low time): this is for the duty cycle, 50% is generated by the PLL or by common clocks but user can adjust this on the constraint if needed. But basing it on the spec 50% is within the 40 to 60% limit of the spec.
3. Tval (output valid from rising edge of the RXCLK or clock-to-out max?): Use this for the set_input_delay -max.
4. Thold (output hold from rising edge of RXCLK or clock-to-out min?): Use ths for the set_input_delay -min.
5. Tsu (Setup time): for the set_output_delay -max.
6. Thold (Hold time): for the set_output_delay -min.


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2. Second step is to analyze the relationship of the clocks of the receive and transmit paths with the data.

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Regarding the difference between the receiving and transmitting path:
1. Receiving path is source-synchronous where RXCLK is an input and comes with the data:
      1.1.Constrain a virtual clock in reference to the PHY chip.
      1.2. User can ignore clock delay here because it’s source-synchronous.
2. Transmitting path is a bit different because TXCLK is an input while the other signals are outputs
      2.1. User would want data to arrive no more than Tsu before the rising clock edge of the virtual clock which is output_delay_max = Tsu + board trace delay.


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See example constraints based on a sample datasheet:

Looking at the datasheet, the input_delay -min/max and output_delay -min/max should be as follow:
• Input setup time (set_input_delay -max) = 28ns
• Input hold time (set_input_delay -min) = 10ns
• Output setup time (set_output_delay -max) = 12ns
• Output hold time (set_output_delay -min) = 0ns


*For the transmit domain, it is not strictly source-synchronous because the clock comes from the PHY chip so the delay of the clock signal should be taken care into account, but usually the delay is very small (almost negligible) if the clock is running at 40ns. 


Draft constraints based on the specs:

//For the RXCLK:
create_clock -name RXCLK_virtual -period <period_value> // Virtual clock for the RX
create_clock -name RXCLK -period <period_value> {get_ports RX_CLK}
set_clock_latency <clock_delay on board to FPGA> {get_clocks RX_CLK} // Can be ignored since it's source synchronous.

//For the TXCLK:
create_generated_clock -name TXCLK -source <clock_source> -divide_by X {get_ports TX_CLK} //assuming it is generated from a clock source
//--OR--
create_clock -name TXCLK_virtual -period <period_value> // Virtual clock for the TX if TX is input
create_clock -name TXCLK -period <period_value> {get_ports TX_CLK} // TX_CLK as input
set_clock_latency <clock_delay on board to FPGA> {get_clocks TX_CLK} // Can be ignored if running at a low speed.


//For the inputs
set_input_delay -clock {get_clocks RXCLK_virtual} -max 28
set_input_delay -clock {get_clocks RXCLK_virtual} -min 10

//For the outputs
set_output_delay -clock {get_clocks TXCLK} -max 12
set_output_delay -clock {get_clocks TXCLK} -min 0


No need for the -clock_fall variant of the constraint MII interface is sampled at the rising edge of the RXCLK and TXCLK.