1774 - Diamond: How can the user set the DELAYB cell to add delay to an input port when a single register exists between the input and output ports?
When only one register is present between the primary input and the primary output ports, that register is automatically placed in the output PIO cell . This prevents the DELAYB cell from being used in the input PIO cell even when user add the DELAYB cell in the HDL code.
To force the map design tool to place the register in the input PIO cell, user need to set the "IO registering" mapping strategy setting to "input' .
There are two ways to get to the "IO registering" map strategy, depending on the Lattice tool being used:
- In the Lattice ispLEVER Project Navigator Process window, right-click on the "Map Design" process and select "Properties"
- In the Lattice Diamond tool, from the File List window, right-click active Strategy, and select "Edit...". In the new window, select "Map Design".
This property is global and will affect all the IO registers. To avoid using this property, user can instead add an extra input register to the design.
User can then set the DIN attribute on the register instance by adding the following preference in the LPF file:
USE DIN TRUE CELL "input_register" ;
Where "input_register" is the instance name of the register.
The preference above will place the added register in the input PIO cell.
Both of the methods described above allow the DELAYB cell ,along with the input register, to be placed in the input PIO cell.
Changing the DELAYB cell DEL* inputs in the HDL code will affect the DI_SET/DI_HLD numbers of the PIO input register in the Place and Route TRACE report.
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